fwbvd1.s

PXA27X_CAYMAN BSP from CAYMAN board

; 
; INTEL CONFIDENTIAL
; Copyright 2000-2003 Intel Corporation All Rights Reserved.
;
; The source code contained or described herein and all documents
; related to the source code (Material) are owned by Intel Corporation
; or its suppliers or licensors.  Title to the Material remains with
; Intel Corporation or its suppliers and licensors. The Material contains
; trade secrets and proprietary and confidential information of Intel
; or its suppliers and licensors. The Material is protected by worldwide
; copyright and trade secret laws and treaty provisions. No part of the
; Material may be used, copied, reproduced, modified, published, uploaded,
; posted, transmitted, distributed, or disclosed in any way without Intel抯
; prior express written permission.

; No license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise. Any license under such intellectual property rights
; must be express and approved by Intel in writing.
;
;
; Module Name:
;
;    fwBvd1.s
;
; Abstract:
;
;    This module implements the code necessary to initialize the HW and
;    Kernel interface routines.
;
;
;  Register Useage:  r10 is used to hold the contents of the RCSR throughout this module.
;                      The rest of the registers are fair game.
;
;
;--
    OPT    2   ; disable listing
    INCLUDE kxarm.h
    INCLUDE Bvd1.inc
    INCLUDE Bvd1bd.inc
    INCLUDE xlli_Bulverde_defs.inc
    INCLUDE  xllp_Pm_SleepContext.inc               ; Needed for sleep reset processing


;
; Conditional Includes
;

    OPT 1   ; reenable listing
    ;OPT    128 ; disable listing of macro expansions
    

    IMPORT  xlli_GPIO_init
    IMPORT  xlli_mem_init
    IMPORT  xlli_intr_init
    IMPORT  xlli_clks_init      ; will poke CCCR (so, must do a FCS to get resultant FC).  *Also does RTC config*
    IMPORT  xlli_ost_init
    IMPORT  xlli_pwrmgr_init
    IMPORT  xlli_IMpwr_init

    EXPORT INITGPIO    
    EXPORT INITMEMC
    EXPORT INITINTC    
    EXPORT INITCLKS
    EXPORT INITOST
    EXPORT INITRTC
    EXPORT INITPWRMAN
    EXPORT DISPLAY_FREQS
    EXPORT INITMMU
    EXPORT SCRUB_SDRAM
    EXPORT _LightUp
    EXPORT _LightUpseg7    

    IMPORT DISPLAY_FREQS
	IMPORT XllpPmValidateResumeFromSleep
	IMPORT XllpPmGoToContextRestoration

   
EBOOT_PARTITION_PHY_BASE        EQU     SDRAM_PHY_EBOOT_PARTITION
EBOOT_PARTITION_VIR_C_BASE      EQU     SDRAM_VIR_C_EBOOT_PARTITION
    

    IF :LNOT: :DEF: ETHBOOT     ; see eboot\fwp2.s
     IMPORT KernelStart         ; If using module as CE Bringup (i.e. Eboot handoff)
    ELSE
     IMPORT  main               ; If using module as POR init code
    ENDIF


;************************************************************************
;   StartUp() is the entry point on Reset (all forms of Reset)
;
;   Desription:  StartUp is the first routine executed when powering on
;       the system.  It is also executed first after all forms of XScale
;       resets.  
;       
;       This code is shared between EBOOT and the CE Kernel.  The flag 'ETHBOOT' denotes
;       if the code is built for EBOOT or CE Kernel initialization (.nb0).
;
;       Regardless of the build type, we disable the MMU and caches
;       immediately and flush'em.
;
;       This routine includes all of the necessary board and core-level
;       initialization code to get Mainstone up.
;
;
;************************************************************************

    STARTUPTEXT

    LEAF_ENTRY StartUp

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;  Notes: - MMU assumed to be inactive at this time, so use physical addresses
;;

    ; During Soft Reset with bootloader in place, r1 contains reset reason indicators.
    ; Save r1 (argument) so r1 is available for use
    mov   r10, r1   

    ; If  we're executing as part of an OS image (rather than EBOOT)
    ; and we're executing in RAM (ie. we're part of a .BIN loaded to RAM by EBOOT)
    ; all necessary init should now have been done and the OS can be launched. 
    IF :LNOT: :DEF: ETHBOOT
        b   INITMMU          ; executing in RAM - launch OS (doesn't return)
    ENDIF

     
    
    bl PREINIT                       ; always call, regardless if using xlli 
    bl INITGPIO
    bl _LightUp

    ;=========================
    ;For reasons unknown at this point, GPIO init and/or HEXLEDS init fail with split transactions enabled.
    ;Therefore, the PREINIT routine disables split transactions and it gets turned back on here.
    ;
    ;Enabling split transactions also causes many 'OEMInterruptHandler Invalid interrupt' messages
    ;particularly when the camera is on (int x19) or USB is doing things (int x0b).
    ;The problem isn't yet understood, but it seems that VAL_IRQ in the ICHP register doesn't get set.
    ;This doesn't happen on every interrupt but does happen frequently (~ 1 in 8 interrupts)
    ;Until this is resolved, leave split transactions off.
    ;=========================
    SPLIT_TRAN_ENABLE
  
    bl INITMEMC
	
    ;ldr    r3, =(SLEEP_TYPE_PHYSICAL)
    ;ldr    r1, [r3]
    ;and	  r1,r1,#1
    ;cmp    r1, #SLEEP_TYPE_SOFT_RESET
    ;orreq    r10, r10, #RCSR_GPIO_RESET
    mov     r1,r10
    ldr      r3,=0xFFFFFFFF
    tst	    r1,r3
    orreq    r10, r10, #RCSR_GPIO_RESET
    
    ldr        r3,=RCSR_WDOG_RESET
    tst        r1,r3
    orrne    r10, r10, #RCSR_GPIO_RESET
    
    ; After some basic init, try to resume if sleep reset.

    ldr         r0,  =xlli_PMRCREGS_PHYSICAL_BASE  ; Get the Power Manager base address
    ldr         r0,  [r0, #xlli_PSPR_offset]       ; And the contents of the PSPR
    mov         r1,  r10                           ; Packed RCSR+PSSR

    bl XllpPmValidateResumeFromSleep               ; R0 ..  R6 lost

    cmp         r0,  #0                            ; Zero return: OK to restore
    bne         ResetFailedRestore   ;  Maybe not even a sleep reset.


    ;; NOTE: GPIO reset and sleep-mediated soft reset require the 
    ;;       same handling.  So sleep-based soft reset will return,
    ;;       but #RCSR_GPIO_RESET will be forced in r10 just below.

    ldr    r3, =(SLEEP_TYPE_PHYSICAL)
    ldr    r1, [r3]

    cmp    r1, #SLEEP_TYPE_SOFT_RESET
    bne    Sleep_Reset_Not_SoftReset 

    ; For soft reset, force same execution path as GPIO reset
    ;   Also invalidate checksum and change sleep type at the same time.

    mov    r1, #SLEEP_TYPE_STANDARD
    str    r1, [r3]
    ldr    r3, =(SLEEP_SAVE_PHYSICAL_BASE)  ; checksum always at sleep base addr
    ldr    r1, [r3]             ; Get checksum
    add    r1, r1, #1           ; Change
    str    r1, [r3]             ; Put bad checksum


    ; for now, make Sleep-based Soft Rest look like GPIO reset.
    orr    r10, r10, #RCSR_GPIO_RESET
    b      GOT_GPIO_RESET  

Sleep_Reset_Not_SoftReset
    bl        INITCLKS                 ; switch clk to turbo mode.
    ldr       r0,  =xlli_PMRCREGS_PHYSICAL_BASE  ; Get the Power Manager base address
    ldr       r0,  [r0, #xlli_PSPR_offset]       ;  Phys. addr of save data
    mov       r1,  r10                           ; Packed RCSR+PSSR
	b         XllpPmGoToContextRestoration               ; Never returns.

ResetFailedRestore

    ; A failed resumability check is treated as no sleep
    ldr         r1,  =xlli_RCSR_SMR
    bic         r10, r10, r1                         

    bl  xlli_intr_init
    ;bl INITINTC
    
     
    ;bl  xlli_clks_init      ; will poke CCCR (so, must do a FCS to get resultant FC).  *Also does RTC config*   THE CULPRIT FOR JACKED UP UART!
    bl INITCLKS
  
    ; bl ledflash
    bl  xlli_ost_init
    ;bl INITOST

    
    bl  xlli_pwrmgr_init
    bl  xlli_IMpwr_init


    bl DISPLAY_FREQS
    bl SCRUB_SDRAM
    b  INITMMU

GOT_GPIO_RESET

; cjw.  Not a real GPIO reset, using Sleep for Soft Reset.
;       Some differences in init might be needed.

;         bl INITGPIO          already done
;        bl INITMEMC   ;    Don't need for real GPIO reset, and it steps on things.   Already done for Sleep Soft Reset
        bl xlli_intr_init    ; use for soft reset

        bl INITCLKS    ;  CCCR and OSCC are maintained through GPIO reset.  But init after Sleep Soft Reset

        bl xlli_ost_init     ; use for soft reset

;        bl xlli_pwrmgr_init  ; PCFR, among others. PCFR is not affected by GPIO reset or sleep in an interesting way.

        bl  xlli_IMpwr_init  

        bl DISPLAY_FREQS
                
;;  Read-only and informative after RAM scrub skipped for GPIO reset as well as sleep.        bl DISPLAY_FREQS ; use for soft reset
        b  INITMMU

;???

        
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
PREINIT
        ; ********************************************************************
        ; Set processor into Supervisior mode (SVC) and disable IRQ & FIQ
        ;
        ldr      r0, =(Mode_SVC :OR: NoIntsMask)
        msr      cpsr_c, r0


        ; ********************************************************************
        ; Grab the CPU ID off of CP15, stuff it into Driver Globals
        ;
        mrc     p15, 0, r9, c0, c0, 0              ; Grab CPU ID
        and r9, r9, #0xF                           ; Grab only the lowest nibble as it's all we care about
    
        ; ********************************************************************
        ; Disable the MMU and gang regardless of why we are here.
        ;
        
        ldr     r0, =0x2043             ; enable access to all coprocessors
        mcr p15, 0, r0, c15, c1, 0
        CPWAIT r0

        ldr     r0, =0x00000078         ; get a zero to turn things off (must write bits[6:3] as 1's)
        mcr p15,0,r0,c1,c0,0            ; Turn Off MMU, I&D Caches, WB.
        CPWAIT  r0

        ldr     r0, =0x00000000         ; get a zero to turn things off
        mcr     p15, 0, r0, c8, c7, 0   ; flush (invalidate) I/D tlb's

        mcr     p15, 0, r0, c7, c7, 0   ; flush (invalidate) I/D caches
        
        mcr     p15, 0, r0, c7, c10, 4  ; Drain the write buffer

        nop
        nop
        nop

        mvn    r0, #0                      ; grant manager access to all domains
        mcr    p15, 0, r0, c3, c0, 0  

        ; Split Transactions seem to cause problems during GPIO initialization so disable for now
        SPLIT_TRAN_DISABLE
        
        ; Soft Resets: Info carried in R10.  If soft reset, this could be the second
        ;   time through (if loaded from Eboot).  In that case, r10 will be nonzero,
        ;   so use that to skip redundant operations that would also corrupt r10.

        ands     r10, r10, r10
        beq      got_SOFT_RESET_PREINIT
        
        ; ********************************************************************
        ; Read & Init Reset Cause bits in RCSR.  
        ;
        ldr     r0,  =PWR_BASE_PHYSICAL
        ldr     r10, [r0, #RCSR_OFFSET]

        ; extract the reset cause bits
        ;
        mov     r2,  #RCSR_ALL                  ; Mask RCSR
        and     r10,  r10,  r2                  ; r10 now holds the conditioned Reset Reason

        ; clear the reset cause bits (they're sticky)
        ;
        str     r2,  [r0, #RCSR_OFFSET]


        ; ********************************************************************
        ; Read and store PSSR, too - it will be reset later, after GPIOs are initialized.  
        ; Unclear when we'll need this information, but don't throw a good status away.
        ; **BMAN:  We really should stick this into driver_globs so that we are not so limited on our register usage!!

        ldr     r0,  =PWR_BASE_PHYSICAL
        ldr     r12, [r0, #PSSR_OFFSET]                       
        
        ; Set VIDAE and BIDAE for VDD/Batt Fault --> IDA
        ;
        mov     r1, #(PMCR_BIDAE:OR:PMCR_VIDAE)     ; configure for imprecise dAbort on VDD and BATT Faults.  *Can set up as an intrerrupt if desired*
        str     r1, [r0, #PMCR_OFFSET]        

        ; extract the reset cause bits
        ;
        mov     r2,  #PSSR_VALID_MASK           ; Mask PSSR (All in lower byte)
        and     r12,  r12,  r2                  ; r12 now holds the conditioned PSSR
        mov     r12,  r12,  lsl #16             ; Move to upper half of register
        orr     r10,  r10,  r12                 ; R10 now has RCSR in lower half and PSSR in upper.

got_SOFT_RESET_PREINIT


        mov  pc, lr
        

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
INITGPIO        
        ; ********************************************************************
        ; Set Alternate Functions, etc.  *Note: LEDs (HEX & discrete) are
        ;  inactive until this routine completes.
        ;

        ldr     r1, =GPIO_BASE_PHYSICAL
        
        ; First, Set GPSRx,y,z HIGH for active low outputs...
        ;

        ldr		r2, =0x3
        str     r2, [r1, #GPSR0_OFFSET]