uc390.cc

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

void
cl_uc390::clear_sfr(void)
{
  cl_uc52::clear_sfr();
	  /* SFR   value */
  sfr->write(0x80, 0xff); /* P4     */
  sfr->write(0x81, 0x07); /* SP     */
  sfr->write(0x86, 0x04); /* DPS    */
  sfr->write(0x90, 0xff); /* P1     */
  sfr->write(0x92, 0xbf); /* P4CNT  */
  sfr->write(0x9b, 0xfc); /* ESP    */
  if (flat24_flag)
    sfr->/*write*/set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
  else
    sfr->/*write*/set(ACON, 0xf8); /* ACON   */
  sfr->write(0xa0, 0xff); /* P2     */
  sfr->write(0xa1, 0xff); /* P5     */
  sfr->write(0xa3, 0x09); /* COC    */
  sfr->write(0xb0, 0xff); /* P3     */
  sfr->write(0xb8, 0x80); /* IP     */
  sfr->write(0xc5, 0x10); /* STATUS */
  sfr->write(0xc6, 0x10); /* MCON   */
  sfr->write(0xc7, 0xff); /* TA     */
  sfr->write(0xc9, 0xe4); /* T2MOD  */
  sfr->write(0xd2, 0x2f); /* MCNT1  */
  sfr->write(0xe3, 0x09); /* C1C    */
}


t_mem
cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
{

  if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
      addr >= 0x400000 &&
      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
    {
      addr -= 0x400000;
      id/*type*/ = MEM_IXRAM_ID;
    }
  return cl_51core::read_mem(id/*type*/, addr); /* 24 bit */
}

t_mem
cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
{
  if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
      addr >= 0x400000 &&
      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
    {
      addr -= 0x400000;
      /*type*/id = MEM_IXRAM_ID;
    }
  return cl_51core::get_mem (/*type*/id, addr);
}

void
cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
{
  if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
      addr >= 0x400000 &&
      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
    {
      addr -= 0x400000;
      /*type*/id = MEM_IXRAM_ID;
    }
  cl_51core::write_mem (/*type*/id, addr, val);
}

void
cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
{
  if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
      addr >= 0x400000 &&
      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
    {
      addr -= 0x400000;
      /*type*/id = MEM_IXRAM_ID;
    }
  cl_51core::set_mem (id/*type*/, addr, val);
}

/*
 *____________________________________________________________________________
 */

void
cl_uc390::push_byte (t_mem uc)
{
  t_addr sp;

  sp = sfr->wadd (SP, 1);
  if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
    {
      if (sp == 0) /* overflow SP */
        sfr->wadd (ESP, 1);
      sp += (sfr->read (ESP) & 0x3) * 256;
      write_mem (MEM_IXRAM_ID, sp, uc); // fixme
    }
  else
    {
      class cl_memory_cell *stck;

      stck = iram->get_cell (sp);
      stck->write (uc);
    }
}

t_mem
cl_uc390::pop_byte (void)
{
  t_mem temp;
  t_addr sp;

  if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
    {
      sp = sfr->read (SP);
      sp += (sfr->read (ESP) & 0x3) * 256;
      temp = read_mem (MEM_IXRAM_ID, sp); // fixme
      sp = sfr->wadd (SP, -1);
      if (sp == 0xff) /* underflow SP */
        sfr->wadd (ESP, -1);
      return temp;
    }
  else
    {
      class cl_memory_cell *stck;

      stck = iram->get_cell (sfr->get (SP));
      temp = stck->read();
      sp = sfr->wadd (SP, -1);
      return temp;
    }
}

/*
 * 0xa3 1 24 INC DPTR
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_inc_dptr (uchar code)
{
  ulong dptr;

  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  dptr = sfr->read (ph) * 256 + sfr->read (pl);
  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    dptr += sfr->read (px) *256*256;
  if (dps & 0x80) /* decr set */
    dptr--;
  else
    dptr++;

  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    sfr->write (px, (dptr >> 16) & 0xff);
  sfr->write (ph, (dptr >> 8) & 0xff);
  sfr->write (pl, dptr & 0xff);

  if (dps & 0x20)                      /* auto-switch dptr */
    sfr->write (DPS, dps ^ 1);  /* toggle dual-dptr switch */
  tick (1);
  return resGO;
}

/*
 * 0x73 1 24 JMP @A+DPTR
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_jmp_Sa_dptr (uchar code)
{
  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  PC = rom->validate_address(sfr->read (ph) * 256 + sfr->read (pl) +
			     acc->read());
  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    PC += sfr->read (px) * 256*256;

  tick (1);
  return resGO;
}

/*
 * 0x90 3 24 MOV DPTR,#data
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_mov_dptr_Sdata (uchar code)
{
  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    sfr->write (px, fetch ());
  sfr->write (ph, fetch ());
  sfr->write (pl, fetch ());

  if (dps & 0x20)                      /* auto-switch dptr */
    sfr->write (DPS, dps ^ 1);    /* toggle dual-dptr switch */

  tick (1);
  return resGO;
}


/*
 * 0x93 1 24 MOVC A,@A+DPTR
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_movc_a_Sa_dptr (uchar code)
{
  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    acc->write (rom->read ((sfr->read (px) * 256*256 +
			    sfr->read (ph) * 256 + sfr->read (pl) +
                acc->read())));
  else
    acc->write (rom->read ((sfr->read (ph) * 256 + sfr->read (pl) +
			    acc->read())));

  if (dps & 0x20)                      /* auto-switch dptr */
    sfr->write (DPS, dps ^ 1);  /* toggle dual-dptr switch */

  tick (1);
  return resGO;
}

/*
 * 0xc0 2 24 PUSH addr
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_push (uchar code)
{
  class cl_memory_cell *cell;

  cell = get_direct(fetch());
  t_addr sp_before= sfr->get(SP);
  t_mem data;
  push_byte (data= cell->read());
  class cl_stack_op *so=
    new cl_stack_push(instPC, data, sp_before, sfr->get(SP));
  so->init();
  stack_write(so);
  tick (1);
  return resGO;
}


/*
 * 0xd0 2 24 POP addr
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_pop (uchar code)
{
  class cl_memory_cell *cell;

  t_addr sp_before= sfr->get(SP);
  t_mem data;
  cell = get_direct (fetch());
  cell->write (data= pop_byte());
  class cl_stack_op *so=
    new cl_stack_pop(instPC, data, sp_before, sfr->get(SP));
  so->init();
  stack_read(so);
  tick (1);
  return resGO;
}


/*
 * 0xe0 1 24 MOVX A,@DPTR
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_movx_a_Sdptr (uchar code)
{
  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    acc->write (read_mem (MEM_XRAM_ID,
                sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl)));
  else
    acc->write (read_mem (MEM_XRAM_ID,
                sfr->read (ph) * 256 + sfr->read (pl)));

  if (dps & 0x20)                      /* auto-switch dptr */
    sfr->write (DPS, dps ^ 1);   /* toggle dual-dptr switch */

  tick (1);
  return resGO;
}

/*
 * 0xf0 1 24 MOVX @DPTR,A
 *____________________________________________________________________________
 *
 */

int
cl_uc390::inst_movx_Sdptr_a (uchar code)
{
  uchar pl, ph, px, dps;

  dps = sfr->get (DPS);
  if (dps & 0x01)
    {
      pl = DPL1;
      ph = DPH1;
      px = DPX1;
    }
  else
    {
      pl = DPL;
      ph = DPH;
      px = DPX;
    }

  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
    write_mem (MEM_XRAM_ID,
               sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl),
               acc->read());
  else
    write_mem (MEM_XRAM_ID,
               sfr->read (ph) * 256 + sfr->read (pl),
               acc->read());

  if (dps & 0x20)                      /* auto-switch dptr */
    sfr->write (DPS, dps ^ 1);   /* toggle dual-dptr switch */