glob.cc

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

/*
 * Simulator of microcontrollers (glob.cc)
 *
 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
 * 
 * To contact author send email to [e-mail]
 * Other contributors include:
 *   Karl Bongers [e-mail],
 *   Johan Knol [e-mail]
 */

/* This file is part of microcontroller simulator: ucsim.

UCSIM is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

UCSIM is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with UCSIM; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/*@1@*/

#include <stdio.h>

#include "stypes.h"
#include "glob.h"

/* this needs to match enum definition in glob.h */
char *op_mnemonic_str[] = {
"BAD_OPCODE",
"ADD",
"ADDC",
"ADDS",
"AND",
"ANL",
"ASL",
"ASR",
"BCC",
"BCS",
"BEQ",
"BG",
"BGE",
"BGT",
"BKPT",
"BL",
"BLE",
"BLT",
"BMI",
"BNE",
"BNV",
"BOV",
"BPL",
"BR",
"CALL",
"CJNE",
"CLR",
"CMP",
"CPL",
"DA",
"DIV_w",
"DIV_d",
"DIVU_b",
"DIVU_w",
"DIVU_d",
"DJNZ",
"FCALL",
"FJMP",
"JB",
"JBC",
"JMP",
"JNB",
"JNZ",
"JZ",
"LEA",
"LSR",
"MOV",
"MOVC",
"MOVS",
"MOVX",
"MUL_w",
"MULU_b",
"MULU_w",
"NEG",
"NOP",
"NORM",
"OR",
"ORL",
"POP",
"POPU",
"PUSH",
"PUSHU",
"RESET",
"RET",
"RETI",
"RL",
"RLC",
"RR",
"RRC",
"SETB",
"SEXT",
"SUB",
"SUBB",
"TRAP",
"XCH",
"XOR",
};

/* this is junk, but we need to keep it until main ucSim code
   is cleaned of dis_entry[] references. */
struct dis_entry glob_disass_xa[]= {
  { 0x0000, 0x00ff, ' ', 1, "nop" },
  { 0x0000, 0x00, 0, 0, NULL}
};

/* plan: keep this list in same order as in User Guide(pg 106)
   until all op-codes are defined.  Figure out how to make simulation
   lookup fast later. */
struct xa_dis_entry disass_xa[]= {
 {0,0x0100,0xf700,' ',2,ADD, REG_REG         },  // ADD Rd, Rs                 0 0 0 0 S 0 0 1  d d d d s s s s
 {0,0x0200,0xf708,' ',2,ADD, REG_IREG        },  // ADD Rd, [Rs]               0 0 0 0 S 0 1 0  d d d d 0 s s s
 {0,0x0208,0xf708,' ',2,ADD, IREG_REG        },  // ADD [Rd], Rs               0 0 0 0 S 0 1 0  s s s s 1 d d d
 {0,0x0400,0xf708,' ',3,ADD, REG_IREGOFF8    },  // ADD Rd, [Rs+offset8]       0 0 0 0 S 1 0 0  d d d d 0 s s s
 {0,0x0408,0xf708,' ',3,ADD, IREGOFF8_REG    },  // ADD [Rd+offset8], Rs       0 0 0 0 S 1 0 0  s s s s 1 d d d
 {0,0x0500,0xf708,' ',4,ADD, REG_IREGOFF16   },  // ADD Rd, [Rs+offset16]      0 0 0 0 S 1 0 1  d d d d 0 s s s
 {0,0x0508,0xf708,' ',4,ADD, IREGOFF16_REG   },  // ADD [Rd+offset16], Rs      0 0 0 0 S 1 0 1  s s s s 1 d d d
 {0,0x0300,0xf708,' ',2,ADD, REG_IREGINC     },  // ADD Rd, [Rs+]              0 0 0 0 S 0 1 1  d d d d 0 s s s
 {0,0x0308,0xf708,' ',2,ADD, IREGINC_REG     },  // ADD [Rd+], Rs              0 0 0 0 S 0 1 1  s s s s 1 d d d
 {0,0x0608,0xf708,' ',3,ADD, DIRECT_REG      },  // ADD direct, Rs             0 0 0 0 S 1 1 0  s s s s 1 x x x
 {0,0x0600,0xf708,' ',3,ADD, REG_DIRECT      },  // ADD Rd, direct             0 0 0 0 S 1 1 0  d d d d 0 x x x
 {0,0x9100,0xff0f,' ',3,ADD, REG_DATA8       },  // ADD Rd, #data8             1 0 0 1 0 0 0 1  d d d d 0 0 0 0
 {0,0x9900,0xff0f,' ',4,ADD, REG_DATA16      },  // ADD Rd, #data16            1 0 0 1 1 0 0 1  d d d d 0 0 0 0
 {0,0x9200,0xff8f,' ',3,ADD, IREG_DATA8      },  // ADD [Rd], #data8           1 0 0 1 0 0 1 0  0 d d d 0 0 0 0
 {0,0x9a00,0xff8f,' ',4,ADD, IREG_DATA16     },  // ADD [Rd], #data16          1 0 0 1 1 0 1 0  0 d d d 0 0 0 0
 {0,0x9300,0xff8f,' ',3,ADD, IREGINC_DATA8   },  // ADD [Rd+], #data8          1 0 0 1 0 0 1 1  0 d d d 0 0 0 0
 {0,0x9b00,0xff8f,' ',4,ADD, IREGINC_DATA16  },  // ADD [Rd+], #data16         1 0 0 1 1 0 1 1  0 d d d 0 0 0 0
 {0,0x9400,0xff8f,' ',4,ADD, IREGOFF8_DATA8  },  // ADD [Rd+offset8], #data8   1 0 0 1 0 1 0 0  0 d d d 0 0 0 0
 {0,0x9c00,0xff8f,' ',5,ADD, IREGOFF8_DATA16 },  // ADD [Rd+offset8], #data16  1 0 0 1 1 1 0 0  0 d d d 0 0 0 0
 {0,0x9500,0xff8f,' ',5,ADD, IREGOFF16_DATA8 },  // ADD [Rd+offset16], #data8  1 0 0 1 0 1 0 1  0 d d d 0 0 0 0
 {0,0x9d00,0xff8f,' ',6,ADD, IREGOFF16_DATA16},  // ADD [Rd+offset16], #data16 1 0 0 1 1 1 0 1  0 d d d 0 0 0 0
 {0,0x9600,0xff8f,' ',4,ADD, DIRECT_DATA8    },  // ADD direct, #data8         1 0 0 1 0 1 1 0  0 b b b 0 0 0 0
 {0,0x9e00,0xff8f,' ',5,ADD, DIRECT_DATA16   },  // ADD direct, #data16        1 0 0 1 1 1 1 0  0 b b b 0 0 0 0

 {0,0x1100,0xf700,' ',2,ADDC,REG_REG         },  //ADDC Rd, Rs                 0 0 0 1 S 0 0 1  d d d d s s s s
 {0,0x1200,0xf708,' ',2,ADDC,REG_IREG        },  //ADDC Rd, [Rs]               0 0 0 1 S 0 1 0  d d d d 0 s s s
 {0,0x1208,0xf708,' ',2,ADDC,IREG_REG        },  //ADDC [Rd], Rs               0 0 0 1 S 0 1 0  s s s s 1 d d d
 {0,0x1400,0xf708,' ',3,ADDC,REG_IREGOFF8    },  //ADDC Rd, [Rs+offset8]       0 0 0 1 S 1 0 0  d d d d 0 s s s
 {0,0x1408,0xf708,' ',3,ADDC,IREGOFF8_REG    },  //ADDC [Rd+offset8], Rs       0 0 0 1 S 1 0 0  s s s s 1 d d d
 {0,0x1500,0xf708,' ',4,ADDC,REG_IREGOFF16   },  //ADDC Rd, [Rs+offset16]      0 0 0 1 S 1 0 1  d d d d 0 s s s
 {0,0x1508,0xf708,' ',4,ADDC,IREGOFF16_REG   },  //ADDC [Rd+offset16], Rs      0 0 0 1 S 1 0 1  s s s s 1 d d d
 {0,0x1300,0xf708,' ',2,ADDC,REG_IREGINC     },  //ADDC Rd, [Rs+]              0 0 0 1 S 0 1 1  d d d d 0 s s s