avr.cc

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

    case 0x95e8:
      return(spm(code));
    case 0x95f8:
      return(espm(code));
    case 0x9408:
      return(sec(code));
    case 0x9488:
      return(clc(code));
    case 0x9428:
      return(sen(code));
    case 0x94a8:
      return(cln(code));
    case 0x9418:
      return(sez(code));
    case 0x9498:
      return(clz(code));
    case 0x9478:
     return(sei(code));
    case 0x94f8:
      return(cli(code));
    case 0x9448:
      return(ses(code));
    case 0x94c8:
      return(cls(code));
    case 0x9438:
      return(sev(code));
    case 0x94b8:
      return(clv(code));
    case 0x9468:
      return(set(code));
    case 0x94e8:
      return(clt(code));
    case 0x9458:
      return(seh(code));
    case 0x94d8:
      return(clh(code));
    case 0x0000:
      return(nop(code));
    case 0x9588: case 0x9598:
      return(sleep(code));
    case 0x95a8: case 0x95b8:
      return(wdr(code));
    }
  switch (code & 0xf000)
    {
    case 0x3000: return(cpi_Rd_K(code));
    case 0x4000: return(sbci_Rd_K(code));
    case 0x5000: return(subi_Rd_K(code));
    case 0x6000: return(ori_Rd_K(code));
    case 0x7000: return(andi_Rd_K(code));
    case 0xc000: return(rjmp_k(code));
    case 0xd000: return(rcall_k(code));
    case 0xe000: return(ldi_Rd_K(code));
    }
  switch (code & 0xf000)
    {
    case 0x0000:
      {
	// 0x0...
	switch (code & 0xfc00)
	  {
	  case 0x0000:
	    {
	      switch (code & 0xff00)
		{
		case 0x0100: return(movw_Rd_Rr(code));
		case 0x0200: return(muls_Rd_Rr(code));
		case 0x0300:
		  {
		    switch (code & 0xff88)
		      {
		      case 0x0300: return(mulsu_Rd_Rr(code));
		      case 0x0308: return(fmul_Rd_Rr(code));
		      case 0x0380: return(fmuls_Rd_Rr(code));
		      case 0x0388: return(fmulsu_Rd_Rr(code));
		      }
		    break;
		  }
		  break;
		}
	      break;
	    }
	  case 0x0400: return(cpc_Rd_Rr(code));
	  case 0x0800: return(sbc_Rd_Rr(code));
	  case 0x0c00: return(add_Rd_Rr(code));
	  }
	break;
      }
    case 0x1000:
      {
	// 0x1...
	switch (code & 0xfc00)
	  {
	  case 0x1000: return(cpse_Rd_Rr(code));
	  case 0x1400: return(cp_Rd_Rr(code));
	  case 0x1800: return(sub_Rd_Rr(code));
	  case 0x1c00: return(adc_Rd_Rr(code));
	  }
	break;
      }
    case 0x2000:
      {
	// 0x2...
	switch (code & 0xfc00)
	  {
	  case 0x2000: return(and_Rd_Rr(code));
	  case 0x2400: return(eor_Rd_Rr(code));
	  case 0x2800: return(or_Rd_Rr(code));
	  case 0x2c00: return(mov_Rd_Rr(code));
	}
	break;
      }
    case 0x8000:
      {
	// 0x8...
	switch (code &0xf208)
	  {
	  case 0x8000: return(ldd_Rd_Z_q(code));
	  case 0x8008: return(ldd_Rd_Y_q(code));
	  case 0x8200: return(std_Z_q_Rr(code));
	  case 0x8208: return(std_Y_q_Rr(code));
	  }
	break;
      }
    case 0x9000:
      {
	// 0x9...
	if ((code & 0xff0f) == 0x9509)
	  return(icall(code));
	if ((code & 0xff0f) == 0x9409)
	  return(ijmp(code));
	if ((code & 0xff00) == 0x9600)
	  return(adiw_Rdl_K(code));
	if ((code & 0xff00) == 0x9700)
	  return(sbiw_Rdl_K(code));
	switch (code & 0xfc00)
	  {
	  case 0x9000:
	    {
	      switch (code & 0xfe0f)
		{
		case 0x9000: return(lds_Rd_k(code));
		case 0x9001: return(ld_Rd_ZS(code));
		case 0x9002: return(ld_Rd_SZ(code));
		case 0x9004: return(lpm_Rd_Z(code));
		case 0x9005: return(lpm_Rd_ZS(code));
		case 0x9006: return(elpm_Rd_Z(code));
		case 0x9007: return(elpm_Rd_ZS(code));
		case 0x9009: return(ld_Rd_YS(code));
		case 0x900a: return(ld_Rd_SY(code));
		case 0x900c: return(ld_Rd_X(code));
		case 0x900d: return(ld_Rd_XS(code));
		case 0x900e: return(ld_Rd_SX(code));
		case 0x900f: return(pop_Rd(code));
		case 0x9200: return(sts_k_Rr(code));
		case 0x9201: return(st_ZS_Rr(code));
		case 0x9202: return(st_SZ_Rr(code));
		case 0x9209: return(st_YS_Rr(code));
		case 0x920a: return(st_SY_Rr(code));
		case 0x920c: return(st_X_Rr(code));
		case 0x920d: return(st_XS_Rr(code));
		case 0x920e: return(st_SX_Rr(code));
		case 0x920f: return(push_Rr(code));
		}
	      break;
	    }
	  case 0x9400:
	    {
	      switch (code & 0xfe0f)
		{
		case 0x9400: return(com_Rd(code));
		case 0x9401: return(neg_Rd(code));
		case 0x9402: return(swap_Rd(code));
		case 0x9403: return(inc_Rd(code));
		case 0x9405: return(asr_Rd(code));
		case 0x9406: return(lsr_Rd(code));
		case 0x9407: return(ror_Rd(code));
		case 0x940a: return(dec_Rd(code));
		case 0x940c: case 0x940d: return(jmp_k(code));
		case 0x940e: case 0x940f: return(call_k(code));
		}
	      break;
	    }
	  case 0x9800:
	    {
	      switch (code & 0xff00)
		{
		case 0x9800: return(cbi_A_b(code));
		case 0x9900: return(sbic_P_b(code));
		case 0x9a00: return(sbi_A_b(code));
		case 0x9b00: return(sbis_P_b(code));
		}
	      break;
	    }
	  case 0x9c00: return(mul_Rd_Rr(code));
	  }
	break;
      }
    case 0xa000:
      {
	// 0xa...
	switch (code &0xf208)
	  {
	  case 0xa000: return(ldd_Rd_Z_q(code));
	  case 0xa008: return(ldd_Rd_Y_q(code));
	  case 0xa200: return(std_Z_q_Rr(code));
	  case 0xa208: return(std_Y_q_Rr(code));
	  }
	break;
      }
    case 0xb000:
      {
	// 0xb...
	switch (code & 0xf800)
	  {
	  case 0xb000: return(in_Rd_A(code));
	  case 0xb800: return(out_A_Rr(code));
	  }
	break;
      }
    case 0xe000:
      {
	// 0xe...
	switch (code & 0xff0f)
	  {
	  case 0xef0f: return(ser_Rd(code));
	  }
	break;
      }
    case 0xf000:
      {
	// 0xf...
	switch (code & 0xfc00)
	  {
	  case 0xf000: return(brbs_s_k(code));
	  case 0xf400: return(brbc_s_k(code));
	  case 0xf800: case 0xfc00:
	    {
	      switch (code & 0xfe08)
		{
		case 0xf800: return(bld_Rd_b(code));
		case 0xfa00: return(bst_Rd_b(code));
		case 0xfc00: case 0xfc08: return(sbrc_Rr_b(code));
		case 0xfe00: case 0xfe08: return(sbrs_Rr_b(code));
		}
	      break;
	    }
	  }
	break;
      }
    }
  /*if (PC)
    PC--;
  else
  PC= get_mem_size(MEM_ROM_ID)-1;*/
  class cl_error_unknown_code *e= new cl_error_unknown_code(this);
  error(e);
  return(resGO);
  PC= rom->inc_address(PC, -1);
  //tick(-clock_per_cycle());
  sim->stop(resINV_INST);
  return(resINV_INST);
}


/*
 */

int
cl_avr::push_data(t_mem data)
{
  t_addr sp;
  t_mem spl, sph;
  
  spl= ram->read(SPL);
  sph= ram->read(SPH);
  sp= 0xffff & (256*sph + spl);
  data= ram->write(sp, data);
  sp= 0xffff & (sp-1);
  spl= sp & 0xff;
  sph= (sp>>8) & 0xff;
  ram->write(SPL, spl);
  ram->write(SPH, sph);
  return(resGO);
}

int
cl_avr::push_addr(t_addr addr)
{
  t_addr sp;
  t_mem spl, sph, al, ah;
  
  spl= ram->read(SPL);
  sph= ram->read(SPH);
  sp= 0xffff & (256*sph + spl);
  al= addr & 0xff;
  ah= (addr>>8) & 0xff;
  ram->write(sp, ah);
  sp= 0xffff & (sp-1);
  ram->write(sp, al);
  sp= 0xffff & (sp-1);
  spl= sp & 0xff;
  sph= (sp>>8) & 0xff;
  ram->write(SPL, spl);
  ram->write(SPH, sph);
  return(resGO);
}

int
cl_avr::pop_data(t_mem *data)
{
  t_addr sp;
  t_mem spl, sph;

  spl= ram->read(SPL);
  sph= ram->read(SPH);
  sp= 256*sph + spl;
  sp= 0xffff & (sp+1);
  *data= ram->read(sp);
  spl= sp & 0xff;
  sph= (sp>>8) & 0xff;
  ram->write(SPL, spl);
  ram->write(SPH, sph);

  return(resGO);
}

int
cl_avr::pop_addr(t_addr *addr)
{
  t_addr sp;
  t_mem spl, sph, al, ah;

  spl= ram->read(SPL);
  sph= ram->read(SPH);
  sp= 256*sph + spl;
  sp= 0xffff & (sp+1);
  al= ram->read(sp);
  sp= 0xffff & (sp+1);
  ah= ram->read(sp);
  *addr= ah*256 + al;
  spl= sp & 0xff;
  sph= (sp>>8) & 0xff;
  ram->write(SPL, spl);
  ram->write(SPH, sph);
  
  return(resGO);
}


/*
 * Set Z, N, V, S bits of SREG after logic instructions and some others
 */

void
cl_avr::set_zn0s(t_mem data)
{
  t_mem sreg= ram->get(SREG) & ~BIT_V;
  data= data&0xff;
  if (!data)
    sreg|= BIT_Z;
  else
    sreg&= ~BIT_Z;
  if (data & 0x80)
    sreg|= (BIT_N|BIT_S);
  else
    sreg&= ~(BIT_N|BIT_S);
  ram->set(SREG, sreg);
}


/* End of avr.src/avr.cc */