mcs51reg.h

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

#ifdef CMH4
#undef CMH4
sfr at 0xE5 CMH4        ; // compare register 4 high byte SAB80517 specific
#endif

#ifdef CMH5
#undef CMH5
sfr at 0xE7 CMH5        ; // compare register 5 high byte SAB80517 specific
#endif

#ifdef CMH6
#undef CMH6
sfr at 0xF3 CMH6        ; // compare register 6 high byte SAB80517 specific
#endif

#ifdef CMH7
#undef CMH7
sfr at 0xF5 CMH7        ; // compare register 7 high byte SAB80517 specific
#endif

#ifdef CMH0_AT_0XC9
#undef CMH0_AT_0XC9
sfr at 0xC9 CMH0        ; // Compare high 0, P80C552 specific
#endif

#ifdef CMH1_AT_0XCA
#undef CMH1_AT_0XCA
sfr at 0xCA CMH1        ; // Compare high 1, P80C552 specific
#endif

#ifdef CMH2_AT_0XCB
#undef CMH2_AT_0XCB
sfr at 0xCB CMH2        ; // Compare high 2, P80C552 specific
#endif

#ifdef CML0
#undef CML0
sfr at 0xD2 CML0        ; // compare register 0 low byte SAB80517 specific
#endif

#ifdef CML1
#undef CML1
sfr at 0xD4 CML1        ; // compare register 1 low byte SAB80517 specific
#endif

#ifdef CML2
#undef CML2
sfr at 0xD6 CML2        ; // compare register 2 low byte SAB80517 specific
#endif

#ifdef CML3
#undef CML3
sfr at 0xE2 CML3        ; // compare register 3 low byte SAB80517 specific
#endif

#ifdef CML4
#undef CML4
sfr at 0xE4 CML4        ; // compare register 4 low byte SAB80517 specific
#endif

#ifdef CML5
#undef CML5
sfr at 0xE6 CML5        ; // compare register 5 low byte SAB80517 specific
#endif

#ifdef CML6
#undef CML6
sfr at 0xF2 CML6        ; // compare register 6 low byte SAB80517 specific
#endif

#ifdef CML7
#undef CML7
sfr at 0xF4 CML7        ; // compare register 7 low byte SAB80517 specific
#endif

#ifdef CML0_AT_0XA9
#undef CML0_AT_0XA9
sfr at 0xA9 CML0        ; // Compare low 0, P80C552 specific
#endif

#ifdef CML1_AT_0XAA
#undef CML1_AT_0XAA
sfr at 0xAA CML1        ; // Compare low 1, P80C552 specific
#endif

#ifdef CML2_AT_0XAB
#undef CML2_AT_0XAB
sfr at 0xAB CML2        ; // Compare low 2, P80C552 specific
#endif

#ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
#undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
sfr at 0xD9 CMOD        ;
#define ECF         0x01
#define CPS0        0x02
#define CPS1        0x04
#define WDTE        0x40
#define CIDL        0x80
#endif

#ifdef CMSEL
#undef CMSEL
sfr at 0xF7 CMSEL       ; // compare input select SAB80517
#endif

#ifdef COMCLRH
#undef COMCLRH
sfr at 0xA4 COMCLRH;
#endif

#ifdef COMCLRL
#undef COMCLRL
sfr at 0xA3 COMCLRL;
#endif

#ifdef COMSETH
#undef COMSETH
sfr at 0xA2 COMSETH;
#endif

#ifdef COMSETL
#undef COMSETL
sfr at 0xA1 COMSETL;
#endif

#ifdef COR
#undef COR
sfr at 0xCE COR         ; // Dallas DS80C390 specific
#define CLKOE       0x01
#define COD0        0x02
#define COD1        0x04
#define C0BPR6      0x08
#define C0BPR7      0x10
#define C1BPR6      0x20
#define C1BPR7      0x40
#define IRDACK      0x80
#endif

#ifdef CRC
#undef CRC
sfr at 0xC1 CRC         ; // Dallas DS5001 specific
#define CRC_        0x01
#define MDM         0x02
#define RNGE0       0x10
#define RNGE1       0x20
#define RNGE2       0x40
#define RNGE3       0x80
#endif

#ifdef CRCH
#undef CRCH
sfr at 0xCB CRCH        ; // compare/reload/capture register, high byte SAB80515 specific
#endif

#ifdef CRCHIGH
#undef CRCHIGH
sfr at 0xC3 CRCHIGH     ; // DS5001 specific
#endif

#ifdef CRCL
#undef CRCL
sfr at 0xCA CRCL        ; // compare/reload/capture register, low byte SAB80515 specific
#endif

#ifdef CRCLOW
#undef CRCLOW
sfr at 0xC2 CRCLOW      ; // DS5001 specific
#endif

#ifdef CT1COM
#undef CT1COM
sfr at 0xBC CT1COM;
#endif

#ifdef CTCOM_AT_0XE1
#undef CTCOM_AT_0XE1
sfr at 0xE1 CTCON       ; // com.timer control register SAB80517
#endif

#ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
#undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
sfr at 0xEB CTCON       ; // Capture control, P80C552 specific
// Not directly accessible Bits.
#define CTP0        0x01
#define CTN0        0x02
#define CTP1        0x04
#define CTN1        0x08
#define CTP2        0x10
#define CTN2        0x20
#define CTP3        0x40
#define CTN3        0x80
#endif

#ifdef CTH0_AT_0XCC
#undef CTH0_AT_0XCC
sfr at 0xCC CTH0        ; // Capture high 0, P80C552 specific
#endif

#ifdef CTH1_AT_0XCD
#undef CTH1_AT_0XCD
sfr at 0xCD CTH1        ; // Capture high 1, P80C552 specific
#endif

#ifdef CTH2_AT_0XCE
#undef CTH2_AT_0XCE
sfr at 0xCE CTH2        ; // Capture high 2, P80C552 specific
#endif

#ifdef CTH3_AT_0XCF
#undef CTH3_AT_0XCF
sfr at 0xCF CTH3        ; // Capture high 3, P80C552 specific
#endif

#ifdef CTL0_AT_0XAC
#undef CTL0_AT_0XAC
sfr at 0xAC CTL0        ; // Capture low 0, P80C552 specific
#endif

#ifdef CTL1_AT_0XAD
#undef CTL1_AT_0XAD
sfr at 0xAD CTL1        ; // Capture low 1, P80C552 specific
#endif

#ifdef CTL2_AT_0XAE
#undef CTL2_AT_0XAE
sfr at 0xAE CTL2        ; // Capture low 2, P80C552 specific
#endif

#ifdef CTL3_AT_0XAF
#undef CTL3_AT_0XAF
sfr at 0xAF CTL3        ; // Capture low 3, P80C552 specific
#endif

#ifdef CTRELH
#undef CTRELH
sfr at 0xDF CTRELH      ; // com.timer rel register high byte SAB80517
#endif

#ifdef CTRELL
#undef CTRELL
sfr at 0xDE CTRELL      ; // com.timer rel register low byte SAB80517
#endif

#ifdef DAPR__SAB80515
#undef DAPR__SAB80515
sfr at 0xDA DAPR        ; // D/A-converter program register SAB80515 specific
#endif

#ifdef DAPR__SAB80517
#undef DAPR__SAB80517
sfr at 0xDA DAPR        ; // D/A-converter program register SAB80517 specific
#endif

#ifdef DPH
#undef DPH
sfr at 0x83 DPH         ;
sfr at 0x83 DP0H        ;  // Alternate name for AT89S53
#endif

#ifdef DPH1
#undef DPH1
sfr at 0x85 DPH1        ; // DS80C320 specific
sfr at 0x85 DP1H        ; // Alternate name for AT89S53
#endif

#ifdef DPL
#undef DPL
sfr at 0x82 DPL         ;  // Alternate name for AT89S53
sfr at 0x82 DP0L        ;
#endif

#ifdef DPL1
#undef DPL1
sfr at 0x84 DPL1        ; // DS80C320 specific
sfr at 0x84 DP1L        ; // Alternate name for AT89S53
#endif

#ifdef DPS__x__x__x__x__x__x__x__SEL
#undef DPS__x__x__x__x__x__x__x__SEL
sfr at 0x86 DPS         ;
// Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
#define SEL         0x01
#endif

#ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
#undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
sfr at 0x86 DPS         ;
// Not directly accessible DPS Bit. DS89C390 specific
#define SEL         0x01
#define TSL         0x20
#define ID0         0x40
#define ID1         0x80
#endif

#ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
#undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
sfr at 0x86 DPS         ;
// Not directly accessible DPS Bit. DS89C420 specific
#define SEL         0x01
#define AID         0x10
#define TSL         0x20
#define ID0         0x40
#define ID1         0x80
#endif

#ifdef DPSEL
#undef DPSEL
sfr at 0x92 DPSEL       ; // data pointer select register SAB80517
#endif

#ifdef DPX
#undef DPX
sfr at 0x93 DPX1        ; // DS80C390 specific
#endif

#ifdef DPX1
#undef DPX1
sfr at 0x95 DPX1        ; // DS80C390 specific
#endif

#ifdef EECON
#undef EECON
sfr at 0xD2 EECON       ;
#define EEBUSY      0x01
#define EEE         0x02
#define EEPL0       0x10
#define EEPL1       0x20
#define EEPL2       0x40
#define EEPL3       0x80
#define EEPL        0xF0
#endif

#ifdef EETIM
#undef EETIM
sfr at 0xD3 EETIM       ;
#endif

#ifdef EICC1
#undef EICC1
sfr at 0xBF EICC1;
#endif

#ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
#undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
sfr at 0xE8 EIE         ;
// Bit registers DS80C320 specific
sbit at 0xE8 EX2        ;
sbit at 0xE9 EX3        ;
sbit at 0xEA EX4        ;
sbit at 0xEB EX5        ;
sbit at 0xEC EWDI       ;
#endif

#ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
#undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
sfr at 0xE8 EIE         ;
// Bit registers DS80C390 specific
sbit at 0xE8 EX2        ;
sbit at 0xE9 EX3        ;
sbit at 0xEA EX4        ;
sbit at 0xEB EX5        ;
sbit at 0xEC EWDI       ;
sbit at 0xED C1IE       ;
sbit at 0xEE C0IE       ;
sbit at 0xEF CANBIE     ;
#endif

#ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
#undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
sfr at 0xF8 EIP         ;
// Bit registers DS80C320 specific
sbit at 0xF8 PX2        ;
sbit at 0xF9 PX3        ;
sbit at 0xFA PX4        ;
sbit at 0xFB PX5        ;
sbit at 0xFC PWDI       ;
#endif

#ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
#undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
sfr at 0xF8 EIP         ;
// Bit registers DS80C320 specific
sbit at 0xF8 PX2        ;
sbit at 0xF9 PX3        ;
sbit at 0xFA PX4        ;
sbit at 0xFB PX5        ;
sbit at 0xFC PWDI       ;
sbit at 0xFD C1IP       ;
sbit at 0xFE C0IP       ;
sbit at 0xFF CANBIP     ;
#endif

#ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
#undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
sfr at 0xF8 EIP0        ;
// Bit registers DS89C420 specific
sbit at 0xF8 LPX2       ;
sbit at 0xF9 LPX3       ;
sbit at 0xFA LPX4       ;
sbit at 0xFB LPX5       ;
sbit at 0xFC LPWDI      ;
#endif

#ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
#undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
sfr at 0xF1 EIP1        ;
// Not directly accessible Bits DS89C420 specific
#define MPX2        0x01
#define MPX3        0x02
#define MPX4        0x04
#define MPX5        0x08
#define MPWDI       0x10
#endif

#ifdef ESP
#undef ESP
sfr at 0x9B ESP         ;
// Not directly accessible Bits DS80C390 specific
#define ESP_0       0x01
#define ESP_1       0x02
#endif

#ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
sfr at 0x91 EXIF        ;
// Not directly accessible EXIF Bits DS80C320 specific
#define BGS         0x01
#define RGSL        0x02
#define RGMD        0x04
#define IE2         0x10
#define IE3         0x20
#define IE4         0x40
#define IE5         0x80
#endif

#ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
sfr at 0x91 EXIF        ;
// Not directly accessible EXIF Bits DS87C520 specific
#define BGS         0x01
#define RGSL        0x02
#define RGMD        0x04
#define XT_RG       0x08
#define IE2         0x10
#define IE3         0x20
#define IE4         0x40
#define IE5         0x80
#endif

#ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
#undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
sfr at 0x91 EXIF        ;
// Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
#define BGS         0x01
#define RGSL        0x02
#define RGMD        0x04
#define CKRY        0x08
#define IE2         0x10
#define IE3         0x20
#define IE4         0x40
#define IE5         0x80
#endif

#ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
#undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
sfr at 0xD5 FCNTL       ;
// Not directly accessible DS89C420 specific
#define FC0         0x01
#define FC1         0x02
#define FC2         0x04
#define FC3         0x08
#define FERR        0x40
#define FBUSY       0x80
#endif

#ifdef FCON
#undef FCON
sfr at 0xD1 FCON        ;
#define FBUSY       0x01
#define FMOD0       0x02
#define FMOD1       0x04
#define FPS         0x08
#define FPL0        0x10
#define FPL1        0x20
#define FPL2        0x40
#define FPL3        0x80
#define FPL         0xF0
#endif

#ifdef FDATA
#undef FDATA
sfr at 0xD6 FDATA       ;
#endif

#ifdef FMODE
#undef FMODE
sfr at 0xB3 FMODE;
#endif

#ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
#undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
sfr at 0xA8 IE          ;
// Bit registers
sbit at 0xA8 EX0        ;
sbit at 0xA9 ET0        ;
sbit at 0xAA EX1        ;
sbit at 0xAB ET1        ;
sbit at 0xAC ES         ;
sbit at 0xAF EA         ;
#endif

#ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
#undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
sfr at 0xA8 IE          ;
// Bit registers
sbit at 0xA8 EX0        ;
sbit at 0xA9 ET0        ;
sbit at 0xAA EX1        ;
sbit at 0xAB ET1        ;
sbit at 0xAC ES         ;
sbit at 0xAD ET2        ; // Enable timer2 interrupt
sbit at 0xAF EA         ;
#endif // IE

#ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
#undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
sfr at 0xA8 IE          ; // same as IEN0 - Interrupt enable 0, P80C552 specific
sfr at 0xA8 IEN0        ; // alternate name
// Bit registers
sbit at 0xA8 EX0        ;
sbit at 0xA9 ET0        ;
sbit at 0xAA EX1        ;
sbit at 0xAB ET1        ;
sbit at 0xAC ES0        ;
sbit at 0xAD ES1        ;
sbit at 0xAE EAD        ;
sbit at 0xAF EEA        ;
#endif

#ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
#undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
sfr at 0xA8 IE          ;
sbit at 0xA8 EX0        ;
sbit at 0xA9 ET0        ;
sbit at 0xAA EX1        ;
sbit at 0xAB ET1        ;
sbit at 0xAC ES         ;
sbit at 0xAD ET2        ;
sbit at 0xAE EC         ;
sbit at 0xAF EA         ;
#endif

#ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
#undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
sfr at 0xA8 IE          ;
// Bit registers
sbit at 0xA8 EX0        ;
sbit at 0xA9 ET0        ;
sbit at 0xAA EX1        ;
sbit at 0xAB ET1        ;
sbit at 0xAC ES         ;
sbit at 0xAC ES0        ; // Alternate name
sbit at 0xAD ET2        ; // Enable timer2 interrupt
sbit at 0xAE ES1        ;
sbit at 0xAF EA         ;
#endif // IE

#ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
#undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
sfr at 0xA8 IE          ;
sfr at 0xA8 IEN0        ; // Alternate name
// Bit registers for the SAB80