mcs51reg.h

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

#ifdef C0M1C
#undef C0M1C
sfr at 0xAB C0M1C       ; // DS80C390 specific
// Not directly accessible bits
#define DTUP        0x01
#define ROW_TIH     0x02
#define MTRQ        0x04
#define EXTRQ       0x08
#define INTRQ       0x10
#define ERI         0x20
#define ETI         0x40
#define MSRDY       0x80
#endif

#ifdef C0M2C
#undef C0M2C
sfr at 0xAC C0M2C       ; // DS80C390 specific
#endif

#ifdef C0M3C
#undef C0M3C
sfr at 0xAD C0M3C       ; // DS80C390 specific
#endif

#ifdef C0M4C
#undef C0M4C
sfr at 0xAE C0M4C       ; // DS80C390 specific
#endif

#ifdef C0M5C
#undef C0M5C
sfr at 0xAF C0M5C       ; // DS80C390 specific
#endif

#ifdef C0M6C
#undef C0M6C
sfr at 0xB3 C0M6C       ; // DS80C390 specific
#endif

#ifdef C0M7C
#undef C0M7C
sfr at 0xB4 C0M7C       ; // DS80C390 specific
#endif

#ifdef C0M8C
#undef C0M8C
sfr at 0xB5 C0M8C       ; // DS80C390 specific
#endif

#ifdef C0M9C
#undef C0M9C
sfr at 0xB6 C0M9C       ; // DS80C390 specific
#endif

#ifdef C0M10C
#undef C0M10C
sfr at 0xB7 C0M10C      ; // DS80C390 specific
#endif

#ifdef C0M11C
#undef C0M11C
sfr at 0xBB C0M11C      ; // DS80C390 specific
#endif

#ifdef C0M12C
#undef C0M12C
sfr at 0xBC C0M12C      ; // DS80C390 specific
#endif

#ifdef C0M13C
#undef C0M13C
sfr at 0xBD C0M13C      ; // DS80C390 specific
#endif

#ifdef C0M14C
#undef C0M14C
sfr at 0xBE C0M14C      ; // DS80C390 specific
#endif

#ifdef C0M15C
#undef C0M15C
sfr at 0xBF C0M15C      ; // DS80C390 specific
#endif

#ifdef C0RE
#undef C0RE
sfr at 0xA7 C0RE        ; // DS80C390 specific
#endif

#ifdef C0RMS0
#undef C0RMS0
sfr at 0x96 C0RMS0      ; // DS80C390 specific
#endif

#ifdef C0RMS1
#undef C0RMS1
sfr at 0x97 C0RMS1      ; // DS80C390 specific
#endif

#ifdef C0S
#undef C0S
sfr at 0xA4 C0S         ; // DS80C390 specific
// Not directly accessible bits
#define ER0         0x01
#define ER1         0x02
#define ER2         0x04
#define TXS         0x08
#define RXS         0x10
#define WKS         0x20
#define EC96_128    0x40
#define BSS         0x80
#endif

#ifdef C0TE
#undef C0TE
sfr at 0xA6 C0TE        ; // DS80C390 specific
#endif

#ifdef C0TMA0
#undef C0TMA0
sfr at 0x9E C0TMA0      ; // DS80C390 specific
#endif

#ifdef C0TMA1
#undef C0TMA1
sfr at 0x9F C0TMA1      ; // DS80C390 specific
#endif

#ifdef C1C
#undef C1C
sfr at 0xE3 C1C         ; // DS80C390 specific
// Not directly accessible bits
#define SWINT       0x01
#define ERCS        0x02
#define AUTOB       0x04
#define CRST        0x08
#define SIESTA      0x10
#define PDE         0x20
#define STIE        0x40
#define ERIE        0x80
#endif

#ifdef C1IR
#undef C1IR
sfr at 0xE5 C1IR        ; // DS80C390 specific
// Not directly accessible bits
#define INTIN0      0x01
#define INTIN1      0x02
#define INTIN2      0x04
#define INTIN3      0x08
#define INTIN4      0x10
#define INTIN5      0x20
#define INTIN6      0x40
#define INTIN7      0x80
#endif

#ifdef C1IRE
#undef C1IRE
sfr at 0xE7 C1RE        ; // DS80C390 specific
#endif

#ifdef C1M1C
#undef C1M1C
sfr at 0xEB C1M1C       ; // DS80C390 specific
#endif

#ifdef C1M2C
#undef C1M2C
sfr at 0xEC C1M2C       ; // DS80C390 specific
#endif

#ifdef C1M3C
#undef C1M3C
sfr at 0xED C1M3C       ; // DS80C390 specific
#endif

#ifdef C1M4C
#undef C1M4C
sfr at 0xEE C1M4C       ; // DS80C390 specific
#endif

#ifdef C1M5C
#undef C1M5C
sfr at 0xEF C1M5C       ; // DS80C390 specific
#endif

#ifdef C1M6C
#undef C1M6C
sfr at 0xF3 C1M6C       ; // DS80C390 specific
#endif

#ifdef C1M7C
#undef C1M7C
sfr at 0xF4 C1M7C       ; // DS80C390 specific
#endif

#ifdef C1M8C
#undef C1M8C
sfr at 0xF5 C1M8C       ; // DS80C390 specific
#endif

#ifdef C1M9C
#undef C1M9C
sfr at 0xF6 C1M9C       ; // DS80C390 specific
#endif

#ifdef C1M10C
#undef C1M10C
sfr at 0xF7 C1M10C      ; // DS80C390 specific
#endif

#ifdef C1M11C
#undef C1M11C
sfr at 0xFB C1M11C      ; // DS80C390 specific
#endif

#ifdef C1M12C
#undef C1M12C
sfr at 0xFC C1M12C      ; // DS80C390 specific
#endif

#ifdef C1M13C
#undef C1M13C
sfr at 0xFD C1M13C      ; // DS80C390 specific
#endif

#ifdef C1M14C
#undef C1M14C
sfr at 0xFE C1M14C      ; // DS80C390 specific
#endif

#ifdef C1M15C
#undef C1M15C
sfr at 0xFF C1M15C      ; // DS80C390 specific
#endif

#ifdef C1S
#undef C1S
sfr at 0xE4 C1S         ; // DS80C390 specific
// Not directly accessible bits
#define ER0         0x01
#define ER1         0x02
#define ER2         0x04
#define TXS         0x08
#define RXS         0x10
#define WKS         0x20
#define CECE        0x40
#define BSS         0x80
#endif

#ifdef C1ITE
#undef C1ITE
sfr at 0xE6 C1TE        ; // DS80C390 specific
#endif

#ifdef C1RSM0
#undef C1RSM0
sfr at 0xD6 C1RSM0      ; // DS80C390 specific
#endif

#ifdef C1RSM1
#undef C1RSM1
sfr at 0xD7 C1RSM1      ; // DS80C390 specific
#endif

#ifdef C1TMA0
#undef C1TMA0
sfr at 0xDE C1TMA0      ; // DS80C390 specific
#endif

#ifdef C1TMA1
#undef C1TMA1
sfr at 0xDF C1TMA1      ; // DS80C390 specific
#endif

#ifdef CC1
#undef CC1
sfr at 0xC2 CC1;
#endif

#ifdef CC2
#undef CC2
sfr at 0xC4 CC2;
#endif

#ifdef CC3
#undef CC3
sfr at 0xC6 CC3;
#endif

#ifdef CC4
#undef CC4
sfr at 0xCE CC4;
#endif

#ifdef CC4EN
#undef CC4EN
sfr at 0xC9 CC4EN       ; // compare/capture 4 enable register SAB80517 specific
#endif

#ifdef CCAP0H_AT_0XFA
#undef CCAP0H_AT_0XFA
sfr at 0xFA CCAP0H      ;
#endif

#ifdef CCAP1H_AT_0XFB
#undef CCAP1H_AT_0XFB
sfr at 0xFB CCAP1H      ;
#endif

#ifdef CCAP2H_AT_0XFC
#undef CCAP2H_AT_0XFC
sfr at 0xFC CCAP2H      ;
#endif

#ifdef CCAP3H_AT_0XFD
#undef CCAP3H_AT_0XFD
sfr at 0xFD CCAP3H      ;
#endif

#ifdef CCAP4H_AT_0XFE
#undef CCAP4H_AT_0XFE
sfr at 0xFE CCAP4H      ;
#endif

#ifdef CCAP0L_AT_0XEA
#undef CCAP0L_AT_0XEA
sfr at 0xEA CCAP0L      ;
#endif

#ifdef CCAP1L_AT_0XEB
#undef CCAP1L_AT_0XEB
sfr at 0xEB CCAP1L      ;
#endif

#ifdef CCAP2L_AT_0XEC
#undef CCAP2L_AT_0XEC
sfr at 0xEC CCAP2L      ;
#endif

#ifdef CCAP3L_AT_0XED
#undef CCAP3L_AT_0XED
sfr at 0xED CCAP3L      ;
#endif

#ifdef CCAP4L_AT_0XEE
#undef CCAP4L_AT_0XEE
sfr at 0xEE CCAP4L      ;
#endif

#ifdef CCAPM0_AT_0XC2
#undef CCAPM0_AT_0XC2
// P89C668 specific, Capture module:
sfr at 0xC2 CCAPM0      ;
#endif

#ifdef CCAPM0_AT_0XDA
#undef CCAPM0_AT_0XDA
sfr at 0xDA CCAPM0      ;
#define ECCF        0x01
#define PWM         0x02
#define TOG         0x04
#define MAT         0x08
#define CAPN        0x10
#define CAPP        0x20
#define ECOM        0x40
#endif

#ifdef CCAPM1_AT_0XC3
#undef CCAPM1_AT_0XC3
sfr at 0xC3 CCAPM1      ;
#endif

#ifdef CCAPM1_AT_0XDB
#undef CCAPM1_AT_0XDB
sfr at 0xDB CCAPM1      ;
#endif

#ifdef CCAPM2_AT_0XC4
#undef CCAPM2_AT_0XC4
sfr at 0xC4 CCAPM2      ;
#endif

#ifdef CCAPM2_AT_0XDC
#undef CCAPM2_AT_0XDC
sfr at 0x0DC CCAPM2     ;
#endif

#ifdef CCAPM3_AT_0XC5
#undef CCAPM3_AT_0XC5
sfr at 0xC5 CCAPM3      ;
#endif

#ifdef CCAPM3_AT_0XDD
#undef CCAPM3_AT_0XDD
sfr at 0x0DD CCAPM3     ;
#endif

#ifdef CCAPM4_AT_0XDE
#undef CCAPM4_AT_0XDE
sfr at 0x0DE CCAPM4     ;
#endif

#ifdef CCAPM4_AT_0XC6
#undef CCAPM4_AT_0XC6
sfr at 0xC6 CCAPM4      ;
#endif

#ifdef CCEN
#undef CCEN
sfr at 0xC1 CCEN        ; // compare/capture enable register SAB80515 specific
#endif

#ifdef CCH1
#undef CCH1
sfr at 0xC3 CCH1        ; // compare/capture register 1, high byte SAB80515 specific
#endif

#ifdef CCH2
#undef CCH2
sfr at 0xC5 CCH2        ; // compare/capture register 2, high byte SAB80515 specific
#endif

#ifdef CCH3
#undef CCH3
sfr at 0xC7 CCH3        ; // compare/capture register 3, high byte SAB80515 specific
#endif

#ifdef CCH4
#undef CCH4
sfr at 0xCF CCH4        ; // compare/capture register 4, high byte SAB80515 specific
#endif

#ifdef CCL1
#undef CCL1
sfr at 0xC2 CCL1        ; // compare/capture register 1, low byte SAB80515 specific
#endif

#ifdef CCL2
#undef CCL2
sfr at 0xC4 CCL2        ; // compare/capture register 2, low byte SAB80515 specific
#endif

#ifdef CCL3
#undef CCL3
sfr at 0xC6 CCL3        ; // compare/capture register 3, low byte SAB80515 specific
#endif

#ifdef CCL4
#undef CCL4
sfr at 0xCE CCL4        ; // compare/capture register 4, low byte SAB80515 specific
#endif

#ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
#undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
sfr at 0xD8 CCON        ; // T89C51RD2 specific register
// Bit registers
sbit at 0xD8 CCF0       ;
sbit at 0xD9 CCF1       ;
sbit at 0xDA CCF2       ;
sbit at 0xDB CCF3       ;
sbit at 0xDC CCF4       ;
sbit at 0xDE CR         ;
sbit at 0xDF CF         ;
#endif

#ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
#undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
// P89C668 specific, PCA Counter control:
sfr at 0xC0 CCON        ;
// Bit registers
sbit at 0xC0 CCF0       ;
sbit at 0xC1 CCF1       ;
sbit at 0xC2 CCF2       ;
sbit at 0xC3 CCF3       ;
sbit at 0xC4 CCF4       ;
//sbit at 0xC5 -
sbit at 0xC6 CR         ;
sbit at 0xC7 CF         ;
#endif

#ifdef CCR
#undef CCR
sfr at 0xCA CCR;
#endif

#ifdef CH_AT_0XF9
#undef CH_AT_0XF9
sfr at 0xF9 CH          ;
#endif

#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
// P89C668 specific, PCA Counter mode:
sfr at 0xC1 CMOD        ;
// not bit addressable:
#define CIDL        0x80
#define WDTE        0x40
#define CPS1        0x04
#define CPS0        0x02
#define ECF         0x01
#endif

#ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
#undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
sfr at 0x8E CKCON       ; // DS80C320 & DS80C390 specific
// Not directly accessible Bits.
#define MD0         0x01
#define MD1         0x02
#define MD2         0x04
#define T0M         0x08
#define T1M         0x10
#define T2M         0x20
#define WD0         0x40
#define WD1         0x80
#endif

#ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
#undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
sfr at 0x8F CKCON       ;
#define X2          0x01
#define T0X2        0x02
#define T1X2        0x04
#define T2X2        0x08
#define SiX2        0x10
#define PcaX2       0x20
#define WdX2        0x40
#endif

#ifdef CKMOD
#undef CKMOD
sfr at 0x96 CKMOD       ; // DS89C420 specific
// Not directly accessible Bits.
#define T0MH        0x08
#define T1MH        0x10
#define T2MH        0x20
#endif

#ifdef CL_AT_0XE9
#undef CL_AT_0XE9
sfr at 0xE9 CL          ;
#endif

#ifdef CLRMSK
#undef CLRMSK
sfr at 0xA6 CLRMSK;
#endif

#ifdef CMEN
#undef CMEN
sfr at 0xF6 CMEN        ; // compare enable register SAB80517 specific
#endif

#ifdef CMH0
#undef CMH0
sfr at 0xD3 CMH0        ; // compare register 0 high byte SAB80517 specific
#endif

#ifdef CMH1
#undef CMH1
sfr at 0xD5 CMH1        ; // compare register 1 high byte SAB80517 specific
#endif

#ifdef CMH2
#undef CMH2
sfr at 0xD7 CMH2        ; // compare register 2 high byte SAB80517 specific
#endif

#ifdef CMH3
#undef CMH3
sfr at 0xE3 CMH3        ; // compare register 3 high byte SAB80517 specific
#endif