mcs51reg.h

sdcc是为51等小型嵌入式cpu设计的c语言编译器支持数种不同类型的cpu

#define SP
#define DPL
#define DPH
#define PCON__SMOD__x__x__x__x__x__x__x
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
#define SCON
#define SBUF
#define P2
#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
#define P3
#define PSW
#define ACC
#define B
// SAB80515 specific registers
#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
#define IRCON
#define CCEN
#define CCL1
#define CCH1
#define CCL2
#define CCH2
#define CCL3
#define CCH3
#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#define CRCL
#define CRCH
#define TL2
#define TH2
#define ADCON
#define ADDAT
#define DAPR__SAB80515
#define P4_AT_0XE8
#define P5_AT_0XF8
#define P6_AT_0XDB
#endif
// end of definitions for the Infineon / Siemens SAB80515


// definitions for the Infineon / Siemens SAB80515A
#ifdef MICROCONTROLLER_SAB80515A
#ifdef MICROCONTROLLER_DEFINED
#define MCS51REG_ERROR
#endif
#ifndef MICROCONTROLLER_DEFINED
#define MICROCONTROLLER_DEFINED
#endif
#ifdef MCS51REG_ENABLE_WARNINGS
#warning Selected HW: Infineon / Siemens SAB80515A
#endif
// 8051 register set without IP
#define P0
#define SP
#define DPL
#define DPH
#define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
#define SCON
#define SBUF
#define P2
#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
#define P3
#define PSW
#define ACC
#define B
// SAB80515A specific registers
#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
#define IRCON
#define CCEN
#define CCL1
#define CCH1
#define CCL2
#define CCH2
#define CCL3
#define CCH3
#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#define CRCL
#define CRCH
#define TL2
#define TH2
#define ADCON0
#define ADDATH
#define ADDATL
#define ADCON1
#define SRELL
#define SYSCON
#define SRELH
#define P4_AT_0XE8
#define P5_AT_0XF8
#define P6_AT_0XDB
#define XPAGE
#endif
// end of definitions for the Infineon / Siemens SAB80515A


// definitions for the Infineon / Siemens SAB80517
#ifdef MICROCONTROLLER_SAB80517
#ifdef MICROCONTROLLER_DEFINED
#define MCS51REG_ERROR
#endif
#ifndef MICROCONTROLLER_DEFINED
#define MICROCONTROLLER_DEFINED
#endif
#ifdef MCS51REG_ENABLE_WARNINGS
#warning Selected HW: Infineon / Siemens SAB80517
#endif
// 8051 register set without IP, SCON & SBUF
#define P0
#define SP
#define DPL
#define DPH
#define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
// #define SCON
// #define SBUF
#define P2
#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
#define P3
#define PSW
#define ACC
#define B
// SAB80517 specific registers
#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
#define IEN2__SAB80517
#define IRCON
#define CCEN
#define CCL1
#define CCH1
#define CCL2
#define CCH2
#define CCL3
#define CCH3
#define CCL4
#define CCH4
#define CC4EN
#define CMEN
#define CMH0
#define CML0
#define CMH1
#define CML1
#define CMH2
#define CML2
#define CMH3
#define CML3
#define CMH4
#define CML4
#define CMH5
#define CML5
#define CMH6
#define CML6
#define CMH7
#define CML7
#define CMSEL
#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
#define CRCL
#define CRCH
#define CTCOM_AT_0XE1
#define CTRELH
#define CTRELL
#define TL2
#define TH2
#define ADCON0
#define ADCON1
#define ADDAT
#define DAPR__SAB80517
#define P4_AT_0XE8
#define P5_AT_0XF8
#define P6_AT_0XFA
#define P7_AT_0XDB
#define P8_AT_0XDD
#define DPSEL
#define ARCON
#define MD0
#define MD1
#define MD2
#define MD3
#define MD4
#define MD5
#define S0BUF
#define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
#define S0RELH
#define S0RELL
#define S1BUF
#define S1CON_AT_0X9B
#define S1RELH
#define S1RELL
#define WDTH
#define WDTL
#define WDTREL
#endif
// end of definitions for the Infineon / Siemens SAB80517


// definitions for the Atmel T89C51RD2
#ifdef MICROCONTROLLER_T89C51RD2
#ifdef MICROCONTROLLER_DEFINED
#define MCS51REG_ERROR
#endif
#ifndef MICROCONTROLLER_DEFINED
#define MICROCONTROLLER_DEFINED
#endif
#ifdef MCS51REG_ENABLE_WARNINGS
#warning Selected HW: T89C51RD2
#endif

// 8051 register set
#define P0
#define SP
#define DPL
#define DPH
#define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
#define SCON
#define SBUF
#define P2
#define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
#define SADDR
#define P3
#define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
#define PSW
#define ACC
#define B

// 8052 register set
#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
#define RCAP2L
#define RCAP2H
#define TL2
#define TH2

// T89C51RD2 register set
#define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
#define P5_AT_0XE8
#define SADEN0

#define AUXR1__x__x__x__x__GF3__x__x__DPS
#define WDTRST_AT_0XA6
#define WDTPRG_AT_0XA7
#define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
#define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
#define FCON
#define EECON
#define EETIM
#define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
#define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
#define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
#define CCAPM0_AT_0XDA
#define CCAPM1_AT_0XDB
#define CCAPM2_AT_0XDC
#define CCAPM3_AT_0XDD
#define CCAPM4_AT_0XDE
#define CL_AT_0XE9
#define CCAP0L_AT_0XEA
#define CCAP1L_AT_0XEB
#define CCAP2L_AT_0XEC
#define CCAP3L_AT_0XED
#define CCAP4L_AT_0XEE
#define CH_AT_0XF9
#define CCAP0H_AT_0XFA
#define CCAP1H_AT_0XFB
#define CCAP2H_AT_0XFC
#define CCAP3H_AT_0XFD
#define CCAP4H_AT_0XFE
#endif /* MICROCONTROLLER_T89C51RD2 */
/* end of definition for the Atmel T89C51RD2 */


/////////////////////////////////////////////////////////
///  don't specify microcontrollers below this line!  ///
/////////////////////////////////////////////////////////


// default microcontroller -> 8051
// use default if no microcontroller specified
#ifndef MICROCONTROLLER_DEFINED
#define MICROCONTROLLER_DEFINED
#ifdef MCS51REG_ENABLE_WARNINGS
#warning No microcontroller defined!
#warning Code generated for the 8051
#endif
// 8051 register set
#define P0
#define SP
#define DPL
#define DPH
#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
#define SCON
#define SBUF
#define P2
#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
#define P3
#define IP__x__x__x__PS__PT1__PX1__PT0__PX0
#define PSW
#define ACC
#define B
#endif
// end of definitions for the default microcontroller


#ifdef MCS51REG_ERROR
#error Two or more microcontrollers defined!
#endif

#ifdef MCS51REG_EXTERNAL_ROM
#ifndef MCS51REG_UNDEFINE_P0
#define MCS51REG_UNDEFINE_P0
#endif
#ifndef MCS51REG_UNDEFINE_P2
#define MCS51REG_UNDEFINE_P2
#endif
#endif

#ifdef MCS51REG_EXTERNAL_RAM
#ifndef MCS51REG_UNDEFINE_P0
#define MCS51REG_UNDEFINE_P0
#endif
#ifndef MCS51REG_UNDEFINE_P2
#define MCS51REG_UNDEFINE_P2
#endif
#endif

#ifdef MCS51REG_UNDEFINE_P0
#undef P0
#endif

#ifdef MCS51REG_UNDEFINE_P2
#undef P2
#endif

////////////////////////////////
///  Register definitions    ///
///  (In alphabetical order) ///
////////////////////////////////

#ifdef ACC
#undef ACC
sfr at 0xE0 ACC         ;
#endif

#ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
#undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
sfr at 0x9D ACON        ; // DS89C420 specific
// Not directly accessible bits
#define PAGES0      0x20
#define PAGES1      0x40
#define PAGEE       0x80
#endif

#ifdef ACON__x__x__x__x__x__SA__AM1__AM0
#undef ACON__x__x__x__x__x__SA__AM1__AM0
sfr at 0x9D ACON        ; // DS89C390 specific
// Not directly accessible bits
#define AM0         0x01
#define AM1         0x02
#define SA          0x04
#endif

#ifdef ADCH_AT_0XC6
#undef ADCH_AT_0XC6
sfr at 0xC6 ADCH        ; // A/D converter high
#endif

#ifdef ADCON
#undef ADCON
sfr at 0xD8 ADCON       ; // A/D-converter control register SAB80515 specific
// Bit registers
sbit at 0xD8 MX0        ;
sbit at 0xD9 MX1        ;
sbit at 0xDA MX2        ;
sbit at 0xDB ADM        ;
sbit at 0xDC BSY        ;
sbit at 0xDE CLK        ;
sbit at 0xDF BD         ;
#endif

// ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
#ifdef ADCON0
#undef ADCON0
sfr at 0xD8 ADCON0      ; // A/D-converter control register 0 SAB80515A &
// Bit registers          // SAB80517 specific
sbit at 0xD8 MX0        ;
sbit at 0xD9 MX1        ;
sbit at 0xDA MX2        ;
sbit at 0xDB ADM        ;
sbit at 0xDC BSY        ;
sbit at 0xDD ADEX       ;
sbit at 0xDE CLK        ;
sbit at 0xDF BD         ;
// Not directly accessible ADCON0
#define ADCON0_MX0  0x01
#define ADCON0_MX1  0x02
#define ADCON0_MX2  0x04
#define ADCON0_ADM  0x08
#define ADCON0_BSY  0x10
#define ADCON0_ADEX 0x20
#define ADCON0_CLK  0x40
#define ADCON0_BD   0x80
#endif

#ifdef ADCON1
#undef ADCON1
sfr at 0xDC ADCON1      ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
// Not directly accessible ADCON1
#define ADCON1_MX0  0x01
#define ADCON1_MX1  0x02
#define ADCON1_MX2  0x04
#define ADCON1_ADCL 0x80
#endif

#ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
#undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
sfr at 0xC5 ADCON       ; // A/D control, P80C552 specific
// Not directly accessible Bits.
#define AADR0       0x01
#define AADR1       0x02
#define AADR2       0x04
#define ADCS        0x08
#define ADCI        0x10
#define ADEX        0x20
#define ADC_0       0x40    // different name as ADC0 in P5
#define ADC_1       0x80    // different name as ADC1 in P5
#endif

#ifdef ADDAT
#undef ADDAT
sfr at 0xD9 ADDAT       ; // A/D-converter data register SAB80515 specific
#endif

#ifdef ADDATH
#undef ADDATH
sfr at 0xD9 ADDATH      ; // A/D data high byte SAB80515A specific
#endif

#ifdef ADDATL
#undef ADDATL
sfr at 0xDA ADDATL      ; // A/D data low byte SAB80515A specific
#endif

#ifdef ARCON
#undef ARCON
sfr at 0xEF ARCON       ; // arithmetic control register SAB80517
#endif

#ifdef AP
#undef AP
sfr at 0x9C AP          ; // DS80C390
#endif

#ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
#undef AUXR__x__x__x__x__x__x__EXTRAM__A0
// P89C668 specific, Auxilary
sfr at 0x8E AUXR        ;
// not bit addressable:
#define EXTRAM      0x02
#define A0          0x01
#endif

#ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
#undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
sfr at 0x8E AUXR        ;
#define AO          0x01
#define EXTRAM      0x02
#define XRS0        0x04
#define XRS1        0x08
#define M0          0x20
#endif
#ifdef B
#undef B
sfr at 0xF0 B           ;
// Bit registers
sbit at 0xF0 BREG_F0    ;
sbit at 0xF1 BREG_F1    ;
sbit at 0xF2 BREG_F2    ;
sbit at 0xF3 BREG_F3    ;
sbit at 0xF4 BREG_F4    ;
sbit at 0xF5 BREG_F5    ;
sbit at 0xF6 BREG_F6    ;
sbit at 0xF7 BREG_F7    ;
#endif

#ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
#undef AUXR1__x__x__x__x__GF3__x__x__DPS
sfr at 0xA2 AUXR1       ;
#define DPS         0x01
#define GF3         0x08
#endif

#ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
#undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
// P89C668 specific, Auxilary 1
sfr at 0xA2 AUXR1       ;
#define ENBOOT      0x20
#define GF2         0x08
#define ALWAYS_ZERO 0x04
#define DPS         0x01
#endif

#ifdef BP2
#undef BP2
sfr at 0xC3 BP2         ;
// Not directly accessible bits
#define MS0         0x01
#define MS1         0x02
#define MS2         0x04
#define LB1         0x08
#define LB2         0x10
#define LB3         0x20
#endif

#ifdef C0C
#undef C0C
sfr at 0xA3 C0C         ; // DS80C390 specific
// Not directly accessible bits
#define SWINT       0x01
#define ERCS        0x02
#define AUTOB       0x04
#define CRST        0x08
#define SIESTA      0x10
#define PDE         0x20
#define STIE        0x40
#define ERIE        0x80
#endif

#ifdef C0IR
#undef C0IR
sfr at 0xA5 C0IR        ; // DS80C390 specific
// Not directly accessible bits
#define INTIN0      0x01
#define INTIN1      0x02
#define INTIN2      0x04
#define INTIN3      0x08
#define INTIN4      0x10
#define INTIN5      0x20
#define INTIN6      0x40
#define INTIN7      0x80
#endif