📄 c8051f120.h
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__sfr __at (0x8B) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */__sfr __at (0x8C) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */__sfr __at (0x8D) PLL0DIV ; /* PLL 0 DIVIDER */__sfr __at (0x8E) PLL0MUL ; /* PLL 0 MULTIPLIER */__sfr __at (0x8F) PLL0FLT ; /* PLL 0 FILTER */__sfr __at (0x96) SFRPGCN ; /* SFR PAGE CONTROL */__sfr __at (0x97) CLKSEL ; /* SYSTEM CLOCK SELECT */__sfr __at (0x9A) CCH0MA ; /* CACHE MISS ACCUMULATOR */__sfr __at (0x9C) P4MDOUT ; /* PORT 4 OUTPUT MODE */__sfr __at (0x9D) P5MDOUT ; /* PORT 5 OUTPUT MODE */__sfr __at (0x9E) P6MDOUT ; /* PORT 6 OUTPUT MODE */__sfr __at (0x9F) P7MDOUT ; /* PORT 7 OUTPUT MODE */__sfr __at (0xA1) CCH0CN ; /* CACHE CONTROL */__sfr __at (0xA2) CCH0TN ; /* CACHE TUNING REGISTER */__sfr __at (0xA3) CCH0LC ; /* CACHE LOCK */__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE */__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE */__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */__sfr __at (0xAD) P1MDIN ; /* PORT 1 INPUT MODE */__sfr __at (0xB7) FLACL ; /* FLASH ACCESS LIMIT */__sfr __at (0xC8) P4 ; /* PORT 4 */__sfr __at (0xD8) P5 ; /* PORT 5 */__sfr __at (0xE1) XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */__sfr __at (0xE2) XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */__sfr __at (0xE3) XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */__sfr __at (0xE8) P6 ; /* PORT 6 */__sfr __at (0xF8) P7 ; /* PORT 7 *//* WORD/DWORD Registers *//* Page 0x00 */__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */__sfr16 __at (0xFAF9) PCA0 ; /* PCA 0 TIMER COUNTER */__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE WORD */__sfr16 __at (0xFEFD) PCA0CP1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE WORD */__sfr16 __at (0xEAE9) PCA0CP2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE WORD */__sfr16 __at (0xECEB) PCA0CP3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE WORD */__sfr16 __at (0xEEED) PCA0CP4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE WORD */__sfr16 __at (0xE2E1) PCA0CP5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE WORD *//* Page 0x01 */__sfr16 __at (0xCDCC) TMR3 ; /* TIMER 3 COUNTER */__sfr16 __at (0xCBCA) RCAP3 ; /* TIMER 3 CAPTURE REGISTER WORD */__sfr16 __at (0xD3D2) DAC1 ; /* DAC 1 REGISTER WORD *//* Page 0x02 */__sfr16 __at (0xCDCC) TMR4 ; /* TIMER 4 COUNTER */__sfr16 __at (0xCBCA) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD *//* Page 0x03 */__sfr16 __at (0xC2C1) MAC0A ; /* MAC0 A Register */ /* No sfr16 definition for MAC0B because MAC0BL must be written last */__sfr32 __at (0x96959493) MAC0ACC ; /* MAC0 Accumulator */__sfr16 __at (0xCFCE) MAC0RND ; /* MAC0 Rounding Register *//* BIT Registers *//* P0 0x80 */__sbit __at (0x80) P0_0 ;__sbit __at (0x81) P0_1 ;__sbit __at (0x82) P0_2 ;__sbit __at (0x83) P0_3 ;__sbit __at (0x84) P0_4 ;__sbit __at (0x85) P0_5 ;__sbit __at (0x86) P0_6 ;__sbit __at (0x87) P0_7 ;/* TCON 0x88 */__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG *//* CPT0CN 0x88 */__sbit __at (0x88) CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */__sbit __at (0x89) CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */__sbit __at (0x8A) CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */__sbit __at (0x8B) CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */__sbit __at (0x8C) CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */__sbit __at (0x8D) CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */__sbit __at (0x8E) CP0OUT ; /* COMPARATOR 0 OUTPUT */__sbit __at (0x8F) CP0EN ; /* COMPARATOR 0 ENABLE *//* CPT1CN 0x88 */__sbit __at (0x88) CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */__sbit __at (0x89) CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */__sbit __at (0x8A) CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */__sbit __at (0x8B) CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */__sbit __at (0x8C) CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */__sbit __at (0x8D) CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */__sbit __at (0x8E) CP1OUT ; /* COMPARATOR 1 OUTPUT */__sbit __at (0x8F) CP1EN ; /* COMPARATOR 1 ENABLE *//* FLSTAT 0x88 */__sbit __at (0x88) FLHBUSY ; /* FLASH BUSY *//* P1 0x90 */__sbit __at (0x90) P1_0 ;__sbit __at (0x91) P1_1 ;__sbit __at (0x92) P1_2 ;__sbit __at (0x93) P1_3 ;__sbit __at (0x94) P1_4 ;__sbit __at (0x95) P1_5 ;__sbit __at (0x96) P1_6 ;__sbit __at (0x97) P1_7 ;/* SCON0 0x98 */__sbit __at (0x98) RI0 ; /* UART 0 RX INTERRUPT FLAG */__sbit __at (0x98) RI ; /* UART 0 RX INTERRUPT FLAG */__sbit __at (0x99) TI0 ; /* UART 0 TX INTERRUPT FLAG */__sbit __at (0x99) TI ; /* UART 0 TX INTERRUPT FLAG */__sbit __at (0x9A) RB80 ; /* UART 0 RX BIT 8 */__sbit __at (0x9B) TB80 ; /* UART 0 TX BIT 8 */__sbit __at (0x9C) REN0 ; /* UART 0 RX ENABLE */__sbit __at (0x9C) REN ; /* UART 0 RX ENABLE */__sbit __at (0x9D) SM20 ; /* UART 0 MULTIPROCESSOR EN */__sbit __at (0x9E) SM10 ; /* UART 0 MODE 1 */__sbit __at (0x9F) SM00 ; /* UART 0 MODE 0 *//* SCON1 0x98 */__sbit __at (0x98) RI1 ; /* UART 1 RX INTERRUPT FLAG */__sbit __at (0x99) TI1 ; /* UART 1 TX INTERRUPT FLAG */__sbit __at (0x9A) RB81 ; /* UART 1 RX BIT 8 */__sbit __at (0x9B) TB81 ; /* UART 1 TX BIT 8 */__sbit __at (0x9C) REN1 ; /* UART 1 RX ENABLE */__sbit __at (0x9D) MCE1 ; /* UART 1 MCE */__sbit __at (0x9F) S1MODE ; /* UART 1 MODE *//* P2 0xA0 */__sbit __at (0xA0) P2_0 ;__sbit __at (0xA1) P2_1 ;__sbit __at (0xA2) P2_2 ;__sbit __at (0xA3) P2_3 ;__sbit __at (0xA4) P2_4 ;__sbit __at (0xA5) P2_5 ;__sbit __at (0xA6) P2_6 ;__sbit __at (0xA7) P2_7 ;/* IE 0xA8 */__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */__sbit __at (0xAC) ES0 ; /* UART0 INTERRUPT ENABLE */__sbit __at (0xAC) ES ; /* UART0 INTERRUPT ENABLE */__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE *//* P3 0xB0 */__sbit __at (0xB0) P3_0 ;__sbit __at (0xB1) P3_1 ;__sbit __at (0xB2) P3_2 ;__sbit __at (0xB3) P3_3 ;__sbit __at (0xB4) P3_4 ;__sbit __at (0xB5) P3_5 ;__sbit __at (0xB6) P3_6 ;__sbit __at (0xB7) P3_7 ;/* IP 0xB8 */__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */⌨️ 快捷键说明
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