📄 c8051f120.h
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/*--------------------------------------------------------------------------- Register Declarations for the Cygnal/SiLabs C8051F12x-F13x Processor Range Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA---------------------------------------------------------------------------*/#ifndef C8051F120_H#define C8051F120_H/* BYTE Registers *//* All Pages */__sfr __at (0x80) P0 ; /* PORT 0 */__sfr __at (0x81) SP ; /* STACK POINTER */__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */__sfr __at (0x84) SFRPAGE ; /* SFR PAGE SELECT */__sfr __at (0x85) SFRNEXT ; /* SFR STACK NEXT PAGE */__sfr __at (0x86) SFRLAST ; /* SFR STACK LAST PAGE */__sfr __at (0x87) PCON ; /* POWER CONTROL */__sfr __at (0x90) P1 ; /* PORT 1 */__sfr __at (0xA0) P2 ; /* PORT 2 */__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */__sfr __at (0xB0) P3 ; /* PORT 3 */__sfr __at (0xB1) PSBANK ; /* FLASH BANK SELECT */__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */__sfr __at (0xE0) ACC ; /* ACCUMULATOR */__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */__sfr __at (0xF0) B ; /* B REGISTER */__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL *//* Page 0x00 */__sfr __at (0x88) TCON ; /* TIMER CONTROL */__sfr __at (0x89) TMOD ; /* TIMER MODE */__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */__sfr __at (0x8E) CKCON ; /* TIMER 0/1 CLOCK CONTROL */__sfr __at (0x8F) PSCTL ; /* FLASH WRITE/ERASE CONTROL */__sfr __at (0x91) SSTA0 ; /* UART 0 STATUS */__sfr __at (0x98) SCON0 ; /* UART 0 CONTROL */__sfr __at (0x98) SCON ; /* UART 0 CONTROL */__sfr __at (0x99) SBUF0 ; /* UART 0 BUFFER */__sfr __at (0x99) SBUF ; /* UART 0 BUFFER */__sfr __at (0x9A) SPI0CFG ; /* SPI 0 CONFIGURATION */__sfr __at (0x9B) SPI0DAT ; /* SPI 0 DATA */__sfr __at (0x9D) SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */__sfr __at (0xA1) EMI0TC ; /* EMIF TIMING CONTROL */__sfr __at (0xA2) EMI0CN ; /* EMIF CONTROL */__sfr __at (0xA2) _XPAGE ; /* XDATA/PDATA PAGE */__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */__sfr __at (0xA9) SADDR0 ; /* UART 0 SLAVE ADDRESS */__sfr __at (0xB7) FLSCL ; /* FLASH SCALE */__sfr __at (0xB9) SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */__sfr __at (0xC9) TMR2CF ; /* TIMER 2 CONFIGURATION */__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */__sfr __at (0xDA) PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */__sfr __at (0xDB) PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */__sfr __at (0xDC) PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */__sfr __at (0xDD) PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */__sfr __at (0xDE) PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */__sfr __at (0xDF) PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */__sfr __at (0xE1) PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xE2) PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */__sfr __at (0xE9) PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xEA) PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */__sfr __at (0xEB) PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xEC) PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */__sfr __at (0xED) PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xEE) PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */__sfr __at (0xF8) SPI0CN ; /* SPI 0 CONTROL */__sfr __at (0xF9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */__sfr __at (0xFA) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */__sfr __at (0xFB) PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xFC) PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */__sfr __at (0xFD) PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */__sfr __at (0xFE) PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE *//* Page 0x01 */__sfr __at (0x88) CPT0CN ; /* COMPARATOR 0 CONTROL */__sfr __at (0x89) CPT0MD ; /* COMPARATOR 0 CONFIGURATION */__sfr __at (0x98) SCON1 ; /* UART 1 CONTROL */__sfr __at (0x99) SBUF1 ; /* UART 1 BUFFER */__sfr __at (0xC8) TMR3CN ; /* TIMER 3 CONTROL */__sfr __at (0xC9) TMR3CF ; /* TIMER 3 CONFIGURATION */__sfr __at (0xCA) RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */__sfr __at (0xCB) RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */__sfr __at (0xCC) TMR3L ; /* TIMER 3 - LOW BYTE */__sfr __at (0xCD) TMR3H ; /* TIMER 3 - HIGH BYTE */__sfr __at (0xD2) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */__sfr __at (0xD3) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */__sfr __at (0xD4) DAC1CN ; /* DAC 1 CONTROL *//* Page 0x02 */__sfr __at (0x88) CPT1CN ; /* COMPARATOR 1 CONTROL */__sfr __at (0x89) CPT1MD ; /* COMPARATOR 1 CONFIGURATION */__sfr __at (0xBA) AMX2CF ; /* ADC 2 MUX CONFIGURATION */__sfr __at (0xBB) AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */__sfr __at (0xBC) ADC2CF ; /* ADC 2 CONFIGURATION */__sfr __at (0xBE) ADC2 ; /* ADC 2 DATA */__sfr __at (0xC4) ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */__sfr __at (0xC6) ADC2LT ; /* ADC 2 LESS-THAN REGISTER */__sfr __at (0xC8) TMR4CN ; /* TIMER 4 CONTROL */__sfr __at (0xC9) TMR4CF ; /* TIMER 4 CONFIGURATION */__sfr __at (0xCA) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */__sfr __at (0xCB) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */__sfr __at (0xCC) TMR4L ; /* TIMER 4 - LOW BYTE */__sfr __at (0xCD) TMR4H ; /* TIMER 4 - HIGH BYTE */__sfr __at (0xE8) ADC2CN ; /* ADC 2 CONTROL *//* Page 0x03 */__sfr __at (0x91) MAC0BL ; /* MAC0 B Register Low Byte */__sfr __at (0x92) MAC0BH ; /* MAC0 B Register High Byte */__sfr __at (0x93) MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */__sfr __at (0x94) MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */__sfr __at (0x95) MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */__sfr __at (0x96) MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */__sfr __at (0x97) MAC0OVR ; /* MAC0 Accumulator Overflow */__sfr __at (0xC0) MAC0STA ; /* MAC0 Status Register */__sfr __at (0xC1) MAC0AL ; /* MAC0 A Register Low Byte */__sfr __at (0xC2) MAC0AH ; /* MAC0 A Register High Byte */__sfr __at (0xC3) MAC0CF ; /* MAC0 Configuration */__sfr __at (0xCE) MAC0RNDL ; /* MAC0 Rounding Register Low Byte */__sfr __at (0xCF) MAC0RNDH ; /* MAC0 Rounding Register High Byte *//* Page 0x0F */__sfr __at (0x88) FLSTAT ; /* FLASH STATUS */__sfr __at (0x89) PLL0CN ; /* PLL 0 CONTROL */__sfr __at (0x8A) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */⌨️ 快捷键说明
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