📄 c8051f410.h
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__sbit __at (0x81) P0_1 ;__sbit __at (0x82) P0_2 ;__sbit __at (0x83) P0_3 ;__sbit __at (0x84) P0_4 ;__sbit __at (0x85) P0_5 ;__sbit __at (0x86) P0_6 ;__sbit __at (0x87) P0_7 ;/* TCON 0x88 */__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG *//* P1 0x90 */__sbit __at (0x90) P1_0 ;__sbit __at (0x91) P1_1 ;__sbit __at (0x92) P1_2 ;__sbit __at (0x93) P1_3 ;__sbit __at (0x94) P1_4 ;__sbit __at (0x95) P1_5 ;__sbit __at (0x96) P1_6 ;__sbit __at (0x97) P1_7 ;/* SCON 0x98 */__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 *//* P2 0xA0 */__sbit __at (0xA0) P2_0 ;__sbit __at (0xA1) P2_1 ;__sbit __at (0xA2) P2_2 ;__sbit __at (0xA3) P2_3 ;__sbit __at (0xA4) P2_4 ;__sbit __at (0xA5) P2_5 ;__sbit __at (0xA6) P2_6 ;__sbit __at (0xA7) P2_7 ;/* IE 0xA8 */__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE *//* P0ODEN 0xB0 */__sbit __at (0xB0) P0OD_0 ; /* P0ODEN.0 - PORT0.0 OVERDRIVE ENABLE */__sbit __at (0xB1) P0OD_1 ; /* P0ODEN.1 - PORT0.1 OVERDRIVE ENABLE */__sbit __at (0xB2) P0OD_2 ; /* P0ODEN.2 - PORT0.2 OVERDRIVE ENABLE */__sbit __at (0xB3) P0OD_3 ; /* P0ODEN.3 - PORT0.3 OVERDRIVE ENABLE */__sbit __at (0xB4) P0OD_4 ; /* P0ODEN.4 - PORT0.4 OVERDRIVE ENABLE */__sbit __at (0xB5) P0OD_5 ; /* P0ODEN.5 - PORT0.5 OVERDRIVE ENABLE */__sbit __at (0xB6) P0OD_6 ; /* P0ODEN.6 - PORT0.6 OVERDRIVE ENABLE */__sbit __at (0xB7) P0OD_7 ; /* P0ODEN.7 - PORT0.7 OVERDRIVE ENABLE *//* IP 0xB8 */__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY *//* SMB0CN 0xC0 */__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR *//* TMR2CN 0xC8 */__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */__sbit __at (0xC9) T2RCLK ; /* TMR2CN.1 - TIMER 2 CAPTURE MODE */__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */__sbit __at (0xCD) TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG *//* PSW 0xD0 */__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG *//* PCA0CN 0xD8 */__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */__sbit __at (0xDD) CCF5 ; /* PCA0CN.5 - PCA MODULE 5 CAPTURE/COMPARE FLAG */__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG *//* ADC0CN 0xE8 */__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */__sbit __at (0xEA) AD0LJST ; /* ADC0CN.2 - ADC 0 LEFT JUSTIFY SELECT */__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */__sbit __at (0xEE) BURSTEN ; /* ADC0CN.6 - ADC 0 BURST MODE ENABLE */__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE *//* SPI0CN 0xF8 */__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG *//* Predefined SFR Bit Masks */#define PCON_IDLE 0x01 /* PCON */#define PCON_STOP 0x02 /* PCON */#define T1M 0x08 /* CKCON */#define PSWE 0x01 /* PSCTL */#define PSEE 0x02 /* PSCTL */#define ECP0 0x20 /* EIE1 */#define PORSF 0x02 /* RSTSRC */#define SWRSF 0x10 /* RSTSRC */#define ECCF 0x01 /* PCA0CPMn */#define PWM 0x02 /* PCA0CPMn */#define TOG 0x04 /* PCA0CPMn */#define MAT 0x08 /* PCA0CPMn */#define CAPN 0x10 /* PCA0CPMn */#define CAPP 0x20 /* PCA0CPMn */#define ECOM 0x40 /* PCA0CPMn */#define PWM16 0x80 /* PCA0CPMn */#define CP0E 0x10 /* XBR0 */#define CP0OEN 0x10 /* XBR0 */#define CP0AE 0x20 /* XBR0 */#define CP0AOEN 0x20 /* XBR0 *//* Interrupts */#define INT_EXT0 0 // External Interrupt 0#define INT_TIMER0 1 // Timer0 Overflow#define INT_EXT1 2 // External Interrupt 1#define INT_TIMER1 3 // Timer1 Overflow#define INT_UART0 4 // Serial Port 0#define INT_TIMER2 5 // Timer2 Overflow#define INT_SPI0 6 // Serial Peripheral Interface 0#define INT_SMBUS0 7 // SMBus0 Interface#define INT_RTC0 8 // RTC0 Interface#define INT_ADC0_WINDOW 9 // ADC0 Window Comparison#define INT_ADC0_EOC 10 // ADC0 End Of Conversion#define INT_PCA0 11 // PCA0 Peripheral#define INT_COMPARATOR0 12 // Comparator0#define INT_COMPARATOR1 13 // Comparator1#define INT_TIMER3 14 // Timer3 Overflow#define INT_VREG_DROPOUT 15 // VREG dropout#define INT_PORT_MATCH 16 // Port Match#endif⌨️ 快捷键说明
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