📄 c8051f000.h
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__sbit __at (0x85) P0_5 ;__sbit __at (0x84) P0_4 ;__sbit __at (0x83) P0_3 ;__sbit __at (0x82) P0_2 ;__sbit __at (0x81) P0_1 ;__sbit __at (0x80) P0_0 ;/* TCON 0x88 */__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE *//* P1 0x90 */__sbit __at (0x97) P1_7 ;__sbit __at (0x96) P1_6 ;__sbit __at (0x95) P1_5 ;__sbit __at (0x94) P1_4 ;__sbit __at (0x93) P1_3 ;__sbit __at (0x92) P1_2 ;__sbit __at (0x91) P1_1 ;__sbit __at (0x90) P1_0 ;/* SCON 0x98 */__sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */__sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */__sbit __at (0x9C) REN ; /* RECEIVE ENABLE */__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */__sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */__sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG *//* P2 0xA0 */__sbit __at (0xA7) P2_7 ;__sbit __at (0xA6) P2_6 ;__sbit __at (0xA5) P2_5 ;__sbit __at (0xA4) P2_4 ;__sbit __at (0xA3) P2_3 ;__sbit __at (0xA2) P2_2 ;__sbit __at (0xA1) P2_1 ;__sbit __at (0xA0) P2_0 ;/* IE 0xA8 */__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */__sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE *//* P3 0xB0 */__sbit __at (0xB7) P3_7 ;__sbit __at (0xB6) P3_6 ;__sbit __at (0xB5) P3_5 ;__sbit __at (0xB4) P3_4 ;__sbit __at (0xB3) P3_3 ;__sbit __at (0xB2) P3_2 ;__sbit __at (0xB1) P3_1 ;__sbit __at (0xB0) P3_0 ;/* IP 0xB8 */__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY *//* SMB0CN 0xC0 */__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE *//* T2CON 0xC8 */__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT *//* PSW 0xD0 */__sbit __at (0xD7) CY ; /* CARRY FLAG */__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */__sbit __at (0xD5) F0 ; /* USER FLAG 0 */__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */__sbit __at (0xD1) F1 ; /* USER FLAG 1 */__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG *//* PCA0CN 0xD8H */__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG *//* ADC0CN 0xE8H */__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT *//* SPI0CN 0xF8H */__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE *//* Predefined SFR Bit Masks */#define PCON_IDLE 0x01 /* PCON */#define PCON_STOP 0x02 /* PCON */#define TF3 0x80 /* TMR3CN */#define CPFIF 0x10 /* CPTnCN */#define CPRIF 0x20 /* CPTnCN */#define CPOUT 0x40 /* CPTnCN */#define ECCF 0x01 /* PCA0CPMn */#define PWM 0x02 /* PCA0CPMn */#define TOG 0x04 /* PCA0CPMn */#define MAT 0x08 /* PCA0CPMn */#define CAPN 0x10 /* PCA0CPMn */#define CAPP 0x20 /* PCA0CPMn */#define ECOM 0x40 /* PCA0CPMn */#endif⌨️ 快捷键说明
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