📄 pic16f684.h
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//// Register Declarations for Microchip 16F684 Processor////// This header file was automatically generated by://// inc2h.pl V1.6//// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved//// SDCC is licensed under the GNU Public license (GPL) v2. Note that// this license covers the code to the compiler and other executables,// but explicitly does not cover any code or objects generated by sdcc.// We have not yet decided on a license for the run time libraries, but// it will not put any requirements on code linked against it. See:// // http://www.gnu.org/copyleft/gpl/html//// See http://sdcc.sourceforge.net/ for the latest information on sdcc.//// #ifndef P16F684_H#define P16F684_H//// Register addresses.//#define INDF_ADDR 0x0000#define TMR0_ADDR 0x0001#define PCL_ADDR 0x0002#define STATUS_ADDR 0x0003#define FSR_ADDR 0x0004#define PORTA_ADDR 0x0005#define PORTC_ADDR 0x0007#define PCLATH_ADDR 0x000A#define INTCON_ADDR 0x000B#define PIR1_ADDR 0x000C#define TMR1L_ADDR 0x000E#define TMR1H_ADDR 0x000F#define T1CON_ADDR 0x0010#define TMR2_ADDR 0x0011#define T2CON_ADDR 0x0012#define CCPR1L_ADDR 0x0013#define CCPR1H_ADDR 0x0014#define CCP1CON_ADDR 0x0015#define PWM1CON_ADDR 0x0016#define ECCPAS_ADDR 0x0017#define WDTCON_ADDR 0x0018#define CMCON0_ADDR 0x0019#define CMCON1_ADDR 0x001A#define ADRESH_ADDR 0x001E#define ADCON0_ADDR 0x001F#define OPTION_REG_ADDR 0x0081#define TRISA_ADDR 0x0085#define TRISC_ADDR 0x0087#define PIE1_ADDR 0x008C#define PCON_ADDR 0x008E#define OSCCON_ADDR 0x008F#define OSCTUNE_ADDR 0x0090#define ANSEL_ADDR 0x0091#define PR2_ADDR 0x0092#define WPU_ADDR 0x0095#define WPUA_ADDR 0x0095#define IOC_ADDR 0x0096#define IOCA_ADDR 0x0096#define VRCON_ADDR 0x0099#define EEDAT_ADDR 0x009A#define EEDATA_ADDR 0x009A#define EEADR_ADDR 0x009B#define EECON1_ADDR 0x009C#define EECON2_ADDR 0x009D#define ADRESL_ADDR 0x009E#define ADCON1_ADDR 0x009F//// Memory organization.//#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON#pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON#pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1// LIST// P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.// NOLIST// This header file defines configurations, registers, and other useful bits of// information for the PIC16F684 microcontroller. These names are taken to match // the data sheets as closely as possible. // Note that the processor must be selected before this file is // included. The processor may be selected the following ways:// 1. Command line switch:// C:\ MPASM MYFILE.ASM /PIC16F684// 2. LIST directive in the source file// LIST P=PIC16F684// 3. Processor Type entry in the MPASM full-screen interface//==========================================================================//// Revision History////==========================================================================//1.00 03/20/03 Original//1.01 08/04/03 Updated CMCON1 address//1.02 08/05/03 Updated names to match datasheet//1.03 08/11/03 Updated ULPWUE bit name to match datasheet//==========================================================================//// Verify Processor////==========================================================================// IFNDEF __16F684// MESSG "Processor-header file mismatch. Verify selected processor."// ENDIF//==========================================================================//// Register Definitions////==========================================================================#define W 0x0000#define F 0x0001//----- Register Files------------------------------------------------------extern __data __at (INDF_ADDR) volatile char INDF;extern __sfr __at (TMR0_ADDR) TMR0;extern __data __at (PCL_ADDR) volatile char PCL;extern __sfr __at (STATUS_ADDR) STATUS;extern __sfr __at (FSR_ADDR) FSR;extern __sfr __at (PORTA_ADDR) PORTA;extern __sfr __at (PORTC_ADDR) PORTC;extern __sfr __at (PCLATH_ADDR) PCLATH;extern __sfr __at (INTCON_ADDR) INTCON;extern __sfr __at (PIR1_ADDR) PIR1;extern __sfr __at (TMR1L_ADDR) TMR1L; extern __sfr __at (TMR1H_ADDR) TMR1H; extern __sfr __at (T1CON_ADDR) T1CON; extern __sfr __at (TMR2_ADDR) TMR2;extern __sfr __at (T2CON_ADDR) T2CON;extern __sfr __at (CCPR1L_ADDR) CCPR1L;extern __sfr __at (CCPR1H_ADDR) CCPR1H;extern __sfr __at (CCP1CON_ADDR) CCP1CON;extern __sfr __at (PWM1CON_ADDR) PWM1CON;extern __sfr __at (ECCPAS_ADDR) ECCPAS;extern __sfr __at (WDTCON_ADDR) WDTCON;extern __sfr __at (CMCON0_ADDR) CMCON0; extern __sfr __at (CMCON1_ADDR) CMCON1; extern __sfr __at (ADRESH_ADDR) ADRESH; extern __sfr __at (ADCON0_ADDR) ADCON0; extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;extern __sfr __at (TRISA_ADDR) TRISA;extern __sfr __at (TRISC_ADDR) TRISC;extern __sfr __at (PIE1_ADDR) PIE1;extern __sfr __at (PCON_ADDR) PCON;extern __sfr __at (OSCCON_ADDR) OSCCON;extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;extern __sfr __at (ANSEL_ADDR) ANSEL;extern __sfr __at (PR2_ADDR) PR2;extern __sfr __at (WPU_ADDR) WPU;extern __sfr __at (WPUA_ADDR) WPUA;extern __sfr __at (IOC_ADDR) IOC;extern __sfr __at (IOCA_ADDR) IOCA;extern __sfr __at (VRCON_ADDR) VRCON;extern __sfr __at (EEDAT_ADDR) EEDAT; extern __sfr __at (EEDATA_ADDR) EEDATA; extern __sfr __at (EEADR_ADDR) EEADR; extern __sfr __at (EECON1_ADDR) EECON1;extern __sfr __at (EECON2_ADDR) EECON2;extern __sfr __at (ADRESL_ADDR) ADRESL; extern __sfr __at (ADCON1_ADDR) ADCON1;//----- STATUS Bits --------------------------------------------------------//----- INTCON Bits --------------------------------------------------------//----- PIR1 Bits ----------------------------------------------------------//----- T1CON Bits ---------------------------------------------------------//----- T2CON Bits ---------------------------------------------------------//----- CCP1CON Bits -------------------------------------------------------//----- PWM1CON Bits -------------------------------------------------------//----- ECCPAS Bits --------------------------------------------------------//----- WDTCON Bits --------------------------------------------------------//----- CMCON0 Bits -------------------------------------------------------//----- CMCON1 Bits -------------------------------------------------------//----- ADCON0 Bits --------------------------------------------------------//----- OPTION Bits --------------------------------------------------------//----- PIE1 Bits ----------------------------------------------------------//----- PCON Bits ----------------------------------------------------------//----- OSCCON Bits --------------------------------------------------------//----- OSCTUNE Bits -------------------------------------------------------//----- ANSEL --------------------------------------------------------------//----- IOC --------------------------------------------------------------//----- IOCA --------------------------------------------------------------//----- VRCON Bits ---------------------------------------------------------//----- EECON1 -------------------------------------------------------------//----- ADCON1 -------------------------------------------------------------//==========================================================================//// RAM Definition////==========================================================================// __MAXRAM H'FF'// __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'// __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'//==========================================================================//// Configuration Bits////==========================================================================#define _FCMEN_ON 0x3FFF#define _FCMEN_OFF 0x37FF#define _IESO_ON 0x3FFF#define _IESO_OFF 0x3BFF#define _BOD_ON 0x3FFF#define _BOD_NSLEEP 0x3EFF#define _BOD_SBODEN 0x3DFF#define _BOD_OFF 0x3CFF#define _CPD_ON 0x3F7F#define _CPD_OFF 0x3FFF#define _CP_ON 0x3FBF#define _CP_OFF 0x3FFF#define _MCLRE_ON 0x3FFF#define _MCLRE_OFF 0x3FDF#define _PWRTE_OFF 0x3FFF#define _PWRTE_ON 0x3FEF#define _WDT_ON 0x3FFF#define _WDT_OFF 0x3FF7#define _LP_OSC 0x3FF8#define _XT_OSC 0x3FF9#define _HS_OSC 0x3FFA#define _EC_OSC 0x3FFB#define _INTRC_OSC_NOCLKOUT 0x3FFC#define _INTRC_OSC_CLKOUT 0x3FFD#define _EXTRC_OSC_NOCLKOUT 0x3FFE#define _EXTRC_OSC_CLKOUT 0x3FFF#define _INTOSCIO 0x3FFC#define _INTOSC 0x3FFD#define _EXTRCIO 0x3FFE#define _EXTRC 0x3FFF// LIST// ----- ADCON0 bits --------------------typedef union { struct { unsigned char ADON:1; unsigned char GO:1; unsigned char CHS0:1; unsigned char CHS1:1; unsigned char CHS2:1; unsigned char :1; unsigned char VCFG:1; unsigned char ADFM:1; }; struct { unsigned char :1; unsigned char NOT_DONE:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; }; struct { unsigned char :1; unsigned char GO_DONE:1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; unsigned char :1; };} __ADCON0_bits_t;extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;#define ADON ADCON0_bits.ADON#define GO ADCON0_bits.GO#define NOT_DONE ADCON0_bits.NOT_DONE#define GO_DONE ADCON0_bits.GO_DONE#define CHS0 ADCON0_bits.CHS0#define CHS1 ADCON0_bits.CHS1#define CHS2 ADCON0_bits.CHS2#define VCFG ADCON0_bits.VCFG#define ADFM ADCON0_bits.ADFM// ----- CCP1CON bits --------------------typedef union { struct { unsigned char CCP1M0:1; unsigned char CCP1M1:1; unsigned char CCP1M2:1; unsigned char CCP1M3:1; unsigned char DC1B0:1; unsigned char DC1B1:1; unsigned char P1M0:1; unsigned char P1M1:1; };} __CCP1CON_bits_t;extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;#define CCP1M0 CCP1CON_bits.CCP1M0#define CCP1M1 CCP1CON_bits.CCP1M1#define CCP1M2 CCP1CON_bits.CCP1M2#define CCP1M3 CCP1CON_bits.CCP1M3#define DC1B0 CCP1CON_bits.DC1B0#define DC1B1 CCP1CON_bits.DC1B1#define P1M0 CCP1CON_bits.P1M0#define P1M1 CCP1CON_bits.P1M1// ----- CMCON0 bits --------------------typedef union { struct { unsigned char CM0:1; unsigned char CM1:1; unsigned char CM2:1; unsigned char CIS:1; unsigned char C1INV:1; unsigned char C2INV:1; unsigned char C1OUT:1; unsigned char C2OUT:1; };} __CMCON0_bits_t;extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;#define CM0 CMCON0_bits.CM0#define CM1 CMCON0_bits.CM1#define CM2 CMCON0_bits.CM2#define CIS CMCON0_bits.CIS⌨️ 快捷键说明
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