📄 pic16c745.h
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//// Register Declarations for Microchip 16C745 Processor////// This header file was automatically generated by://// inc2h.pl V1.6//// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved//// SDCC is licensed under the GNU Public license (GPL) v2. Note that// this license covers the code to the compiler and other executables,// but explicitly does not cover any code or objects generated by sdcc.// We have not yet decided on a license for the run time libraries, but// it will not put any requirements on code linked against it. See:// // http://www.gnu.org/copyleft/gpl/html//// See http://sdcc.sourceforge.net/ for the latest information on sdcc.//// #ifndef P16C745_H#define P16C745_H//// Register addresses.//#define INDF_ADDR 0x0000#define TMR0_ADDR 0x0001#define PCL_ADDR 0x0002#define STATUS_ADDR 0x0003#define FSR_ADDR 0x0004#define PORTA_ADDR 0x0005#define PORTB_ADDR 0x0006#define PORTC_ADDR 0x0007#define PCLATH_ADDR 0x000A#define INTCON_ADDR 0x000B#define PIR1_ADDR 0x000C#define PIR2_ADDR 0x000D#define TMR1L_ADDR 0x000E#define TMR1H_ADDR 0x000F#define T1CON_ADDR 0x0010#define TMR2_ADDR 0x0011#define T2CON_ADDR 0x0012#define CCPR1L_ADDR 0x0015#define CCPR1H_ADDR 0x0016#define CCP1CON_ADDR 0x0017#define RCSTA_ADDR 0x0018#define TXREG_ADDR 0x0019#define RCREG_ADDR 0x001A#define CCPR2L_ADDR 0x001B#define CCPR2H_ADDR 0x001C#define CCP2CON_ADDR 0x001D#define ADRES_ADDR 0x001E#define ADCON0_ADDR 0x001F#define OPTION_REG_ADDR 0x0081#define TRISA_ADDR 0x0085#define TRISB_ADDR 0x0086#define TRISC_ADDR 0x0087#define PIE1_ADDR 0x008C#define PIE2_ADDR 0x008D#define PCON_ADDR 0x008E#define PR2_ADDR 0x0092#define TXSTA_ADDR 0x0098#define SPBRG_ADDR 0x0099#define ADCON1_ADDR 0x009F#define UIR_ADDR 0x0190#define UIE_ADDR 0x0191#define UEIR_ADDR 0x0192#define UEIE_ADDR 0x0193#define USTAT_ADDR 0x0194#define UCTRL_ADDR 0x0195#define UADDR_ADDR 0x0196#define USWSTAT_ADDR 0x0197#define UEP0_ADDR 0x0198#define UEP1_ADDR 0x0199#define UEP2_ADDR 0x019A#define BD0OST_ADDR 0x01A0#define BD0OBC_ADDR 0x01A1#define BD0OAL_ADDR 0x01A2#define BD0IST_ADDR 0x01A4#define BD0IBC_ADDR 0x01A5#define BD0IAL_ADDR 0x01A6#define BD1OST_ADDR 0x01A8#define BD1OBC_ADDR 0x01A9#define BD1OAL_ADDR 0x01AA#define BD1IST_ADDR 0x01AC#define BD1IBC_ADDR 0x01AD#define BD1IAL_ADDR 0x01AE#define BD2OST_ADDR 0x01B0#define BD2OBC_ADDR 0x01B1#define BD2OAL_ADDR 0x01B2#define BD2IST_ADDR 0x01B4#define BD2IBC_ADDR 0x01B5#define BD2IAL_ADDR 0x01B6//// Memory organization.//#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1#pragma memmap UIR_ADDR UIR_ADDR SFR 0x000 // UIR#pragma memmap UIE_ADDR UIE_ADDR SFR 0x000 // UIE#pragma memmap UEIR_ADDR UEIR_ADDR SFR 0x000 // UEIR#pragma memmap UEIE_ADDR UEIE_ADDR SFR 0x000 // UEIE#pragma memmap USTAT_ADDR USTAT_ADDR SFR 0x000 // USTAT#pragma memmap UCTRL_ADDR UCTRL_ADDR SFR 0x000 // UCTRL#pragma memmap UADDR_ADDR UADDR_ADDR SFR 0x000 // UADDR#pragma memmap USWSTAT_ADDR USWSTAT_ADDR SFR 0x000 // USWSTAT#pragma memmap UEP0_ADDR UEP0_ADDR SFR 0x000 // UEP0#pragma memmap UEP1_ADDR UEP1_ADDR SFR 0x000 // UEP1#pragma memmap UEP2_ADDR UEP2_ADDR SFR 0x000 // UEP2#pragma memmap BD0OST_ADDR BD0OST_ADDR SFR 0x000 // BD0OST#pragma memmap BD0OBC_ADDR BD0OBC_ADDR SFR 0x000 // BD0OBC#pragma memmap BD0OAL_ADDR BD0OAL_ADDR SFR 0x000 // BD0OAL#pragma memmap BD0IST_ADDR BD0IST_ADDR SFR 0x000 // BD0IST#pragma memmap BD0IBC_ADDR BD0IBC_ADDR SFR 0x000 // BD0IBC#pragma memmap BD0IAL_ADDR BD0IAL_ADDR SFR 0x000 // BD0IAL#pragma memmap BD1OST_ADDR BD1OST_ADDR SFR 0x000 // BD1OST#pragma memmap BD1OBC_ADDR BD1OBC_ADDR SFR 0x000 // BD1OBC#pragma memmap BD1OAL_ADDR BD1OAL_ADDR SFR 0x000 // BD1OAL#pragma memmap BD1IST_ADDR BD1IST_ADDR SFR 0x000 // BD1IST#pragma memmap BD1IBC_ADDR BD1IBC_ADDR SFR 0x000 // BD1IBC#pragma memmap BD1IAL_ADDR BD1IAL_ADDR SFR 0x000 // BD1IAL#pragma memmap BD2OST_ADDR BD2OST_ADDR SFR 0x000 // BD2OST#pragma memmap BD2OBC_ADDR BD2OBC_ADDR SFR 0x000 // BD2OBC#pragma memmap BD2OAL_ADDR BD2OAL_ADDR SFR 0x000 // BD2OAL#pragma memmap BD2IST_ADDR BD2IST_ADDR SFR 0x000 // BD2IST#pragma memmap BD2IBC_ADDR BD2IBC_ADDR SFR 0x000 // BD2IBC#pragma memmap BD2IAL_ADDR BD2IAL_ADDR SFR 0x000 // BD2IAL// LIST// P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc.// NOLIST// This header file defines configurations, registers, and other useful bits of// information for the PIC16C745 microcontroller. These names are taken to match // the data sheets as closely as possible. // Note that the processor must be selected before this file is // included. The processor may be selected the following ways:// 1. Command line switch:// C:\ MPASM MYFILE.ASM /PIC16C745// 2. LIST directive in the source file// LIST P=PIC16C745// 3. Processor Type entry in the MPASM full-screen interface//==========================================================================//// Revision History////==========================================================================//Rev: Date: Reason://1.00 28 Sep 99 Initial Release//==========================================================================//// Verify Processor////==========================================================================// IFNDEF __16C745// MESSG "Processor-header file mismatch. Verify selected processor."// ENDIF//==========================================================================//// Register Definitions////==========================================================================#define W 0x0000#define F 0x0001//----- Register Files------------------------------------------------------extern __data __at (INDF_ADDR) volatile char INDF;extern __sfr __at (TMR0_ADDR) TMR0;extern __data __at (PCL_ADDR) volatile char PCL;extern __sfr __at (STATUS_ADDR) STATUS;extern __sfr __at (FSR_ADDR) FSR;extern __sfr __at (PORTA_ADDR) PORTA;extern __sfr __at (PORTB_ADDR) PORTB;extern __sfr __at (PORTC_ADDR) PORTC;extern __sfr __at (PCLATH_ADDR) PCLATH;extern __sfr __at (INTCON_ADDR) INTCON;extern __sfr __at (PIR1_ADDR) PIR1;extern __sfr __at (PIR2_ADDR) PIR2;extern __sfr __at (TMR1L_ADDR) TMR1L;extern __sfr __at (TMR1H_ADDR) TMR1H;extern __sfr __at (T1CON_ADDR) T1CON;extern __sfr __at (TMR2_ADDR) TMR2;extern __sfr __at (T2CON_ADDR) T2CON;extern __sfr __at (CCPR1L_ADDR) CCPR1L;extern __sfr __at (CCPR1H_ADDR) CCPR1H;extern __sfr __at (CCP1CON_ADDR) CCP1CON;extern __sfr __at (RCSTA_ADDR) RCSTA;extern __sfr __at (TXREG_ADDR) TXREG;extern __sfr __at (RCREG_ADDR) RCREG;extern __sfr __at (CCPR2L_ADDR) CCPR2L;extern __sfr __at (CCPR2H_ADDR) CCPR2H;extern __sfr __at (CCP2CON_ADDR) CCP2CON;extern __sfr __at (ADRES_ADDR) ADRES;extern __sfr __at (ADCON0_ADDR) ADCON0;extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;extern __sfr __at (TRISA_ADDR) TRISA;extern __sfr __at (TRISB_ADDR) TRISB;extern __sfr __at (TRISC_ADDR) TRISC;extern __sfr __at (PIE1_ADDR) PIE1;extern __sfr __at (PIE2_ADDR) PIE2;extern __sfr __at (PCON_ADDR) PCON;extern __sfr __at (PR2_ADDR) PR2;extern __sfr __at (TXSTA_ADDR) TXSTA;extern __sfr __at (SPBRG_ADDR) SPBRG;extern __sfr __at (ADCON1_ADDR) ADCON1;extern __sfr __at (UIR_ADDR) UIR;extern __sfr __at (UIE_ADDR) UIE;extern __sfr __at (UEIR_ADDR) UEIR;extern __sfr __at (UEIE_ADDR) UEIE;extern __sfr __at (USTAT_ADDR) USTAT;extern __sfr __at (UCTRL_ADDR) UCTRL;extern __sfr __at (UADDR_ADDR) UADDR;extern __sfr __at (USWSTAT_ADDR) USWSTAT;extern __sfr __at (UEP0_ADDR) UEP0;extern __sfr __at (UEP1_ADDR) UEP1;extern __sfr __at (UEP2_ADDR) UEP2;extern __sfr __at (BD0OST_ADDR) BD0OST;extern __sfr __at (BD0OBC_ADDR) BD0OBC;extern __sfr __at (BD0OAL_ADDR) BD0OAL;extern __sfr __at (BD0IST_ADDR) BD0IST;extern __sfr __at (BD0IBC_ADDR) BD0IBC;extern __sfr __at (BD0IAL_ADDR) BD0IAL;extern __sfr __at (BD1OST_ADDR) BD1OST;extern __sfr __at (BD1OBC_ADDR) BD1OBC;extern __sfr __at (BD1OAL_ADDR) BD1OAL;extern __sfr __at (BD1IST_ADDR) BD1IST;extern __sfr __at (BD1IBC_ADDR) BD1IBC;extern __sfr __at (BD1IAL_ADDR) BD1IAL;extern __sfr __at (BD2OST_ADDR) BD2OST;extern __sfr __at (BD2OBC_ADDR) BD2OBC;extern __sfr __at (BD2OAL_ADDR) BD2OAL;extern __sfr __at (BD2IST_ADDR) BD2IST;extern __sfr __at (BD2IBC_ADDR) BD2IBC;extern __sfr __at (BD2IAL_ADDR) BD2IAL;//----- STATUS Bits --------------------------------------------------------//----- INTCON Bits --------------------------------------------------------//----- PIR1 Bits ----------------------------------------------------------//----- PIR2 Bits ----------------------------------------------------------//----- T1CON Bits ---------------------------------------------------------//----- T2CON Bits ---------------------------------------------------------//----- CCP1CON Bits -------------------------------------------------------//----- RCSTA Bits ---------------------------------------------------------//----- CCP2CON Bits -------------------------------------------------------//----- ADCON0 Bits --------------------------------------------------------//----- OPTION Bits --------------------------------------------------------⌨️ 快捷键说明
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