📄 pic16f914.h
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//// Register Declarations for Microchip 16F914 Processor////// This header file was automatically generated by://// inc2h.pl V1.6//// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved//// SDCC is licensed under the GNU Public license (GPL) v2. Note that// this license covers the code to the compiler and other executables,// but explicitly does not cover any code or objects generated by sdcc.// We have not yet decided on a license for the run time libraries, but// it will not put any requirements on code linked against it. See:// // http://www.gnu.org/copyleft/gpl/html//// See http://sdcc.sourceforge.net/ for the latest information on sdcc.//// #ifndef P16F914_H#define P16F914_H//// Register addresses.//#define INDF_ADDR 0x0000#define TMR0_ADDR 0x0001#define PCL_ADDR 0x0002#define STATUS_ADDR 0x0003#define FSR_ADDR 0x0004#define PORTA_ADDR 0x0005#define PORTB_ADDR 0x0006#define PORTC_ADDR 0x0007#define PORTD_ADDR 0x0008#define PORTE_ADDR 0x0009#define PCLATH_ADDR 0x000A#define INTCON_ADDR 0x000B#define PIR1_ADDR 0x000C#define PIR2_ADDR 0x000D#define TMR1L_ADDR 0x000E#define TMR1H_ADDR 0x000F#define T1CON_ADDR 0x0010#define TMR2_ADDR 0x0011#define T2CON_ADDR 0x0012#define SSPBUF_ADDR 0x0013#define SSPCON_ADDR 0x0014#define CCPR1L_ADDR 0x0015#define CCPR1H_ADDR 0x0016#define CCP1CON_ADDR 0x0017#define RCSTA_ADDR 0x0018#define TXREG_ADDR 0x0019#define RCREG_ADDR 0x001A#define CCPR2L_ADDR 0x001B#define CCPR2H_ADDR 0x001C#define CCP2CON_ADDR 0x001D#define ADRESH_ADDR 0x001E#define ADCON0_ADDR 0x001F#define OPTION_REG_ADDR 0x0081#define TRISA_ADDR 0x0085#define TRISB_ADDR 0x0086#define TRISC_ADDR 0x0087#define TRISD_ADDR 0x0088#define TRISE_ADDR 0x0089#define PIE1_ADDR 0x008C#define PIE2_ADDR 0x008D#define PCON_ADDR 0x008E#define OSCCON_ADDR 0x008F#define OSCTUNE_ADDR 0x0090#define ANSEL_ADDR 0x0091#define PR2_ADDR 0x0092#define SSPADD_ADDR 0x0093#define SSPSTAT_ADDR 0x0094#define WPUB_ADDR 0x0095#define WPU_ADDR 0x0095#define IOCB_ADDR 0x0096#define IOC_ADDR 0x0096#define CMCON1_ADDR 0x0097#define TXSTA_ADDR 0x0098#define SPBRG_ADDR 0x0099#define CMCON0_ADDR 0x009C#define VRCON_ADDR 0x009D#define ADRESL_ADDR 0x009E#define ADCON1_ADDR 0x009F#define WDTCON_ADDR 0x0105#define LCDCON_ADDR 0x0107#define LCDPS_ADDR 0x0108#define LVDCON_ADDR 0x0109#define EEDATL_ADDR 0x010C#define EEADRL_ADDR 0x010D#define EEDATH_ADDR 0x010E#define EEADRH_ADDR 0x010F#define LCDDATA0_ADDR 0x0110#define LCDDATA1_ADDR 0x0111#define LCDDATA2_ADDR 0x0112#define LCDDATA3_ADDR 0x0113#define LCDDATA4_ADDR 0x0114#define LCDDATA5_ADDR 0x0115#define LCDDATA6_ADDR 0x0116#define LCDDATA7_ADDR 0x0117#define LCDDATA8_ADDR 0x0118#define LCDDATA9_ADDR 0x0119#define LCDDATA10_ADDR 0x011A#define LCDDATA11_ADDR 0x011B#define LCDSE0_ADDR 0x011C#define LCDSE1_ADDR 0x011D#define LCDSE2_ADDR 0x011E#define EECON1_ADDR 0x018C#define EECON2_ADDR 0x018D//// Memory organization.//#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON#pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL#pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH#pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0#pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1#pragma memmap LCDDATA2_ADDR LCDDATA2_ADDR SFR 0x000 // LCDDATA2#pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3#pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4#pragma memmap LCDDATA5_ADDR LCDDATA5_ADDR SFR 0x000 // LCDDATA5#pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6#pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7#pragma memmap LCDDATA8_ADDR LCDDATA8_ADDR SFR 0x000 // LCDDATA8#pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9#pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10#pragma memmap LCDDATA11_ADDR LCDDATA11_ADDR SFR 0x000 // LCDDATA11#pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0#pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1#pragma memmap LCDSE2_ADDR LCDSE2_ADDR SFR 0x000 // LCDSE2#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2// LIST// P16F914.INC Standard Header File, Version 1.00 Microchip Technology, Inc.// NOLIST// This header file defines configurations, registers, and other useful bits of// information for the PIC16F914 microcontroller.// These names are taken to match the data sheets as closely as possible. // Note that the processor must be selected before this file is // included. The processor may be selected the following ways:// 1. Command line switch:// C:\ MPASM MYFILE.ASM /PIC16F914// 2. LIST directive in the source file// LIST P=PIC16F914// 3. Processor Type entry in the MPASM full-screen interface//==========================================================================//// Revision History////==========================================================================//Rev: Date: Reason://1.00 06/11/04 Initial Release//1.01 08/16/04 Added EECON2 //==========================================================================//// Verify Processor////==========================================================================// IFNDEF __16F914// MESSG "Processor-header file mismatch. Verify selected processor."// ENDIF//==========================================================================//// Register Definitions////==========================================================================#define W 0x0000#define F 0x0001//----- Register Files------------------------------------------------------extern __data __at (INDF_ADDR) volatile char INDF;extern __sfr __at (TMR0_ADDR) TMR0;extern __data __at (PCL_ADDR) volatile char PCL;extern __sfr __at (STATUS_ADDR) STATUS;extern __sfr __at (FSR_ADDR) FSR;extern __sfr __at (PORTA_ADDR) PORTA;extern __sfr __at (PORTB_ADDR) PORTB;extern __sfr __at (PORTC_ADDR) PORTC;extern __sfr __at (PORTD_ADDR) PORTD;extern __sfr __at (PORTE_ADDR) PORTE;extern __sfr __at (PCLATH_ADDR) PCLATH;extern __sfr __at (INTCON_ADDR) INTCON;extern __sfr __at (PIR1_ADDR) PIR1;extern __sfr __at (PIR2_ADDR) PIR2;extern __sfr __at (TMR1L_ADDR) TMR1L;extern __sfr __at (TMR1H_ADDR) TMR1H;extern __sfr __at (T1CON_ADDR) T1CON;extern __sfr __at (TMR2_ADDR) TMR2;extern __sfr __at (T2CON_ADDR) T2CON;extern __sfr __at (SSPBUF_ADDR) SSPBUF;extern __sfr __at (SSPCON_ADDR) SSPCON;extern __sfr __at (CCPR1L_ADDR) CCPR1L;extern __sfr __at (CCPR1H_ADDR) CCPR1H;extern __sfr __at (CCP1CON_ADDR) CCP1CON;extern __sfr __at (RCSTA_ADDR) RCSTA;extern __sfr __at (TXREG_ADDR) TXREG;extern __sfr __at (RCREG_ADDR) RCREG;extern __sfr __at (CCPR2L_ADDR) CCPR2L;extern __sfr __at (CCPR2H_ADDR) CCPR2H;extern __sfr __at (CCP2CON_ADDR) CCP2CON;extern __sfr __at (ADRESH_ADDR) ADRESH;extern __sfr __at (ADCON0_ADDR) ADCON0;extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;extern __sfr __at (TRISA_ADDR) TRISA;extern __sfr __at (TRISB_ADDR) TRISB;extern __sfr __at (TRISC_ADDR) TRISC;extern __sfr __at (TRISD_ADDR) TRISD;extern __sfr __at (TRISE_ADDR) TRISE;extern __sfr __at (PIE1_ADDR) PIE1;extern __sfr __at (PIE2_ADDR) PIE2;extern __sfr __at (PCON_ADDR) PCON;extern __sfr __at (OSCCON_ADDR) OSCCON;extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;extern __sfr __at (ANSEL_ADDR) ANSEL;extern __sfr __at (PR2_ADDR) PR2;extern __sfr __at (SSPADD_ADDR) SSPADD;extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;extern __sfr __at (WPUB_ADDR) WPUB;extern __sfr __at (WPU_ADDR) WPU;extern __sfr __at (IOCB_ADDR) IOCB;extern __sfr __at (IOC_ADDR) IOC;extern __sfr __at (CMCON1_ADDR) CMCON1;extern __sfr __at (TXSTA_ADDR) TXSTA;extern __sfr __at (SPBRG_ADDR) SPBRG;extern __sfr __at (CMCON0_ADDR) CMCON0;extern __sfr __at (VRCON_ADDR) VRCON;extern __sfr __at (ADRESL_ADDR) ADRESL;extern __sfr __at (ADCON1_ADDR) ADCON1;extern __sfr __at (WDTCON_ADDR) WDTCON;extern __sfr __at (LCDCON_ADDR) LCDCON;extern __sfr __at (LCDPS_ADDR) LCDPS;extern __sfr __at (LVDCON_ADDR) LVDCON;extern __sfr __at (EEDATL_ADDR) EEDATL;extern __sfr __at (EEADRL_ADDR) EEADRL;extern __sfr __at (EEDATH_ADDR) EEDATH;extern __sfr __at (EEADRH_ADDR) EEADRH;extern __sfr __at (LCDDATA0_ADDR) LCDDATA0;extern __sfr __at (LCDDATA1_ADDR) LCDDATA1;extern __sfr __at (LCDDATA2_ADDR) LCDDATA2;extern __sfr __at (LCDDATA3_ADDR) LCDDATA3;extern __sfr __at (LCDDATA4_ADDR) LCDDATA4;extern __sfr __at (LCDDATA5_ADDR) LCDDATA5;extern __sfr __at (LCDDATA6_ADDR) LCDDATA6;extern __sfr __at (LCDDATA7_ADDR) LCDDATA7;extern __sfr __at (LCDDATA8_ADDR) LCDDATA8;extern __sfr __at (LCDDATA9_ADDR) LCDDATA9;extern __sfr __at (LCDDATA10_ADDR) LCDDATA10;extern __sfr __at (LCDDATA11_ADDR) LCDDATA11;extern __sfr __at (LCDSE0_ADDR) LCDSE0;extern __sfr __at (LCDSE1_ADDR) LCDSE1;extern __sfr __at (LCDSE2_ADDR) LCDSE2;extern __sfr __at (EECON1_ADDR) EECON1;extern __sfr __at (EECON2_ADDR) EECON2;//----- STATUS Bits --------------------------------------------------------//----- INTCON Bits --------------------------------------------------------//----- PIR1 Bits ----------------------------------------------------------//----- PIR2 Bits ----------------------------------------------------------//----- T1CON Bits ---------------------------------------------------------//----- T2CON Bits ---------------------------------------------------------//----- SSPCON Bits --------------------------------------------------------//----- CCP1CON Bits -------------------------------------------------------//----- RCSTA Bits ---------------------------------------------------------//----- CCP2CON Bits -------------------------------------------------------//----- ADCON0 Bits --------------------------------------------------------//----- OPTION Bits -----------------------------------------------------//----- PIE1 Bits ----------------------------------------------------------//----- PIE2 Bits ----------------------------------------------------------//----- PCON Bits ----------------------------------------------------------//----- OSCCON Bits -------------------------------------------------------//----- OSCTUNE Bits -------------------------------------------------------//----- ANSEL Bits ---------------------------------------------------------//----- SSPSTAT Bits -------------------------------------------------------//----- WPUB Bits -------------------------------------------------------//----- WPU Bits -------------------------------------------------------//----- IOCB Bits -------------------------------------------------------//----- IOC Bits -------------------------------------------------------⌨️ 快捷键说明
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