📄 pic18f4331.h
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extern __sfr __at (0xFCF) TMR1H;extern __sfr __at (0xFD0) RCON;typedef union { struct { unsigned BOR : 1; unsigned POR : 1; unsigned PD : 1; unsigned TO : 1; unsigned RI : 1; unsigned : 1; unsigned : 1; unsigned IPEN : 1; };} __RCON_t;extern volatile __RCON_t __at (0xFD0) RCONbits;extern __sfr __at (0xFD1) WDTCON;typedef union { struct { unsigned SWDTEN : 1; unsigned WDT : 7; };} __WDTCON_t;extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;extern __sfr __at (0xFD2) LVDCON;typedef union { struct { unsigned LVDL0 : 1; unsigned LVDL1 : 1; unsigned LVDL2 : 1; unsigned LVDL3 : 1; unsigned LVDEN : 1; unsigned IRVST : 1; unsigned : 1; unsigned : 1; };} __LVDCON_t;extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;extern __sfr __at (0xFD3) OSCCON;typedef union { struct { unsigned SCS : 2; unsigned FLTS : 1; unsigned OSTS : 1; unsigned IRCF : 3; unsigned IDLEN : 1; };} __OSCCON_t;extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;extern __sfr __at (0xFD5) T0CON;typedef union { struct { unsigned T0PS0 : 1; unsigned T0PS1 : 1; unsigned T0PS2 : 1; unsigned T0PS3 : 1; unsigned : 1; unsigned : 1; unsigned _16BIT : 1; unsigned TMR0ON : 1; };} __T0CON_t;extern volatile __T0CON_t __at (0xFD5) T0CONbits;extern __sfr __at (0xFD6) TMR0L;extern __sfr __at (0xFD7) TMR0H;extern __sfr __at (0xFD8) STATUS;typedef union { struct { unsigned C : 1; unsigned DC : 1; unsigned Z : 1; unsigned OV : 1; unsigned N : 1; unsigned : 1; unsigned : 1; unsigned : 1; };} __STATUS_t;extern volatile __STATUS_t __at (0xFD8) STATUSbits;extern __sfr __at (0xFD9) FSR2L;extern __sfr __at (0xFDA) FSR2H;typedef union { struct { unsigned FSR2H : 4; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; };} __FSR2H_t;extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;extern __sfr __at (0xFDB) PLUSW2;extern __sfr __at (0xFDC) PREINC2;extern __sfr __at (0xFDD) POSTDEC2;extern __sfr __at (0xFDE) POSTINC2;extern __sfr __at (0xFDF) INDF2;extern __sfr __at (0xFE0) BSR;typedef union { struct { unsigned BSR : 4; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; };} __BSR_t;extern volatile __BSR_t __at (0xFE0) BSRbits;extern __sfr __at (0xFE1) FSR1L;extern __sfr __at (0xFE2) FSR1H;typedef union { struct { unsigned FSR1H : 4; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; };} __FSR1H_t;extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;extern __sfr __at (0xFE3) PLUSW1;extern __sfr __at (0xFE4) PREINC1;extern __sfr __at (0xFE5) POSTDEC1;extern __sfr __at (0xFE6) POSTINC1;extern __sfr __at (0xFE7) INDF1;extern __sfr __at (0xFE8) WREG;extern __sfr __at (0xFE9) FSR0L;extern __sfr __at (0xFEA) FSR0H;typedef union { struct { unsigned FSR0H : 4; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; };} __FSR0H_t;extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;extern __sfr __at (0xFEB) PLUSW0;extern __sfr __at (0xFEC) PREINC0;extern __sfr __at (0xFED) POSTDEC0;extern __sfr __at (0xFEE) POSTINC0;extern __sfr __at (0xFEF) INDF0;extern __sfr __at (0xFF0) INTCON3;typedef union { struct { unsigned INT1IF : 1; unsigned INT2IF : 1; unsigned : 1; unsigned INT1IE : 1; unsigned INT2IE : 1; unsigned : 1; unsigned INT1IP : 1; unsigned INT2IP : 1; };} __INTCON3_t;extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;extern __sfr __at (0xFF1) INTCON2;typedef union { struct { unsigned RBIP : 1; unsigned : 1; unsigned TMR0IP : 1; unsigned : 1; unsigned INTEDG2 : 1; unsigned INTEDG1 : 1; unsigned INTEDG0 : 1; unsigned RBPU : 1; };} __INTCON2_t;extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;extern __sfr __at (0xFF2) INTCON;typedef union { struct { unsigned RBIF : 1; unsigned INT0IF : 1; unsigned TMR0IF : 1; unsigned RBIE : 1; unsigned INT0IE : 1; unsigned TMR0IE : 1; unsigned PEIE_GIEL : 1; unsigned GIE_GIEH : 1; }; struct { unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned PEIE : 1; unsigned GIE : 1; }; struct { unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned : 1; unsigned GIEL : 1; unsigned GIEH : 1; };} __INTCON_t;extern volatile __INTCON_t __at (0xFF2) INTCONbits;extern __sfr __at (0xFF3) PRODL;extern __sfr __at (0xFF4) PRODH;extern __sfr __at (0xFF5) TABLAT;extern __sfr __at (0xFF6) TBLPTRL;extern __sfr __at (0xFF7) TBLPTRH;extern __sfr __at (0xFF8) TBLPTRU;typedef union { struct { unsigned TBLPTRU : 5; unsigned ACSS : 1; unsigned : 1; unsigned : 1; };} __TBLPTRU_t;extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;extern __sfr __at (0xFF9) PCL;extern __sfr __at (0xFFA) PCLATH;typedef union { struct { unsigned PCH : 8; };} __PCLATH_t;extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;extern __sfr __at (0xFFB) PCLATU;typedef union { struct { unsigned PCU : 5; unsigned : 1; unsigned : 1; unsigned : 1; };} __PCLATU_t;extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;extern __sfr __at (0xFFC) STKPTR;typedef union { struct { unsigned STKPTR : 5; unsigned : 1; unsigned STKUNF : 1; unsigned STKFUL : 1; };} __STKPTR_t;extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;extern __sfr __at (0xFFD) TOSL;extern __sfr __at (0xFFE) TOSH;extern __sfr __at (0xFFF) TOSU;typedef union { struct { unsigned TOSU : 5; unsigned : 1; unsigned : 1; unsigned : 1; };} __TOSU_t;extern volatile __TOSU_t __at (0xFFF) TOSUbits;/* Configuration register locations */#define __CONFIG1H 0x300001#define __CONFIG2L 0x300002#define __CONFIG2H 0x300003#define __CONFIG3L 0x300004#define __CONFIG3H 0x300005#define __CONFIG4L 0x300006#define __CONFIG5L 0x300008#define __CONFIG5H 0x300009#define __CONFIG6L 0x30000A#define __CONFIG6H 0x30000B#define __CONFIG7L 0x30000C#define __CONFIG7H 0x30000D/* Oscillator 1H options */#define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */#define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */#define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */#define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */#define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */#define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */#define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */#define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */#define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */#define _OSC_HS_1H 0xF2 /* HS */#define _OSC_XT_1H 0xF1 /* XT */#define _OSC_LP_1H 0xF0 /* LP *//* Fail-Safe Clock Monitor Enable 1H options */#define _FCMEN_ON_1H 0xFF /* Enabled */#define _FCMEN_OFF_1H 0xBF /* Disabled *//* Internal External Switch Over Mode 1H options */#define _IESO_OFF_1H 0x7F /* Disabled */#define _IESO_ON_1H 0xFF /* Enabled *//* Power Up Timer 2L options */#define _PUT_OFF_2L 0xFF /* Disabled */#define _PUT_ON_2L 0xFE /* Enabled *//* Brown Out Detect 2L options */#define _BODEN_ON_2L 0xFF /* Enabled */#define _BODEN_OFF_2L 0xFD /* Disabled *//* Brown Out Voltage 2L options */#define _BODENV_UNDEFINED_2L 0xFF /* Undefined */#define _BODENV_2_7V_2L 0xFB /* 2.7V */#define _BODENV_4_2V_2L 0xF7 /* 4.2V */#define _BODENV_4_5V_2L 0xF3 /* 4.5V *//* Watchdog Timer 2H options */#define _WDT_ON_2H 0xFF /* Enabled */#define _WDT_OFF_2H 0xFE /* Disabled *//* Watchdog Postscaler 2H options */#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */#define _WDTPS_1_512_2H 0xF3 /* 1:512 */#define _WDTPS_1_256_2H 0xF1 /* 1:256 */#define _WDTPS_1_128_2H 0xEF /* 1:128 */#define _WDTPS_1_64_2H 0xED /* 1:64 */#define _WDTPS_1_32_2H 0xEB /* 1:32 */#define _WDTPS_1_16_2H 0xE9 /* 1:16 */#define _WDTPS_1_8_2H 0xE7 /* 1:8 */#define _WDTPS_1_4_2H 0xE5 /* 1:4 */#define _WDTPS_1_2_2H 0xE3 /* 1:2 */#define _WDTPS_1_1_2H 0xE1 /* 1:1 *//* Watchdog Timer Window 2H options */#define _WINEN_OFF_2H 0xFF /* Disabled */#define _WINEN_ON_2H 0xDF /* Enabled *//* PWM Output Pin Reset 3L options */#define _PWMPIN_PWM_OUTPUTS_OFF_UPON_RESET_3L 0xFF /* PWM outputs disabled upon RESET */#define _PWMPIN_PWM_OUTPUTS_DRIVE_ACTIVE_STATES_UPON_RESET_3L 0xFB /* PWM outputs drive active states upon RESET *//* Low-Side Transistors Polarity 3L options */#define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 0, 2, 4 and 6 are active high */#define _LPOL_PWM_0__2__4_AND_6_ARE_ACTIVE_LOW_3L 0xF7 /* PWM 0, 2, 4 and 6 are active low *//* High-Side Transistors Polarity 3L options */#define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_HIGH_3L 0xFF /* PWM 1, 3, 5, and 7 are active high */#define _HPOL_PWM_1__3__5__AND_7_ARE_ACTIVE_LOW_3L 0xEF /* PWM 1, 3, 5, and 7 are active low *//* Timer1 OSC 3L options */#define _T1OSCMX_LOW_POWER_3L 0xFF /* Low Power */#define _T1OSCMX_LEGACY_3L 0xDF /* Legacy *//* FLTA Mux 3H options */#define _FLTAMX_FLTA_INPUT_MUXED_WITH_RC1_3H 0xFF /* FLTA input muxed with RC1 */#define _FLTAMX_FLTA_INPUT_MUXED_WITH_RD4_3H 0xFE /* FLTA input muxed with RD4 *//* SSP I/O Mux 3H options */#define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RD3__RD2_AND_RD1_RESPECTIVELY__3H 0xFB /* SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively. */#define _SSPMX_SCK_SCL__SDA_SDI_AND_SDO_ARE_MUX_W__RC5__RC4_AND_RC7_RESPECTIVELY__3H 0xFF /* SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively. *//* PWM4 Mux 3H options */#define _PWM4MX_PWM4_OUTPUT_MUXED_W__RB5_3H 0xFF /* PWM4 output muxed w/ RB5 */#define _PWM4MX_PWM4_OUTPUT_MUXED_W__RD5_3H 0xF7 /* PWM4 output muxed w/ RD5 *//* TMR0/T5CKI EXT CLK Mux 3H options */#define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RD0_3H 0xEF /* TMR0/T5CKI external clock input is multiplexed with RD0 */#define _EXCLKMX_TMR0_T5CKI_EXTERNAL_CLOCK_INPUT_IS_MULTIPLEXED_WITH_RC3_3H 0xFF /* TMR0/T5CKI external clock input is multiplexed with RC3 *//* Master Clear Enable 3H options */#define _MCLRE_MCLR_ON__RE3_INPUT_OFF_3H 0xFF /* MCLR enabled, RE3 input disabled */#define _MCLRE_RE3_INPUT_ON__MCLR_OFF_3H 0x7F /* RE3 input enabled, MCLR disabled *//* Background Debug 4L options */#define _BACKBUG_OFF_4L 0xFF /* Disabled */#define _BACKBUG_ON_4L 0x7F /* Enabled *//* Low Voltage Program 4L options */#define _LVP_ON_4L 0xFF /* Enabled */#define _LVP_OFF_4L 0xFB /* Disabled *//* Stack Overflow Reset 4L options */#define _STVR_ON_4L 0xFF /* Enabled */#define _STVR_OFF_4L 0xFE /* Disabled *//* Code Protect 00200-00FFF 5L options */#define _CP_0_OFF_5L 0xFF /* Disabled */#define _CP_0_ON_5L 0xFE /* Enabled *//* Code Protect 01000-01FFF 5L options */#define _CP_1_OFF_5L 0xFF /* Disabled */#define _CP_1_ON_5L 0xFD /* Enabled *//* Code Protect 02000-02FFF 5L options */#define _CP_2_OFF_5L 0xFF /* Disabled */#define _CP_2_ON_5L 0xFB /* Enabled *//* Code Protect 03000-03FFF 5L options */#define _CP_3_OFF_5L 0xFF /* Disabled */#define _CP_3_ON_5L 0xF7 /* Enabled *//* Data EE Read Protect 5H options */#define _CPD_OFF_5H 0xFF /* Disabled */#define _CPD_ON_5H 0x7F /* Enabled *//* Code Protect Boot 5H options */#define _CPB_OFF_5H 0xFF /* Disabled */#define _CPB_ON_5H 0xBF /* Enabled *//* Table Write Protect 00200-00FFF 6L options */#define _WRT_0_OFF_6L 0xFF /* Disabled */#define _WRT_0_ON_6L 0xFE /* Enabled *//* Table Write Protect 01000-01FFF 6L options */#define _WRT_1_OFF_6L 0xFF /* Disabled */#define _WRT_1_ON_6L 0xFD /* Enabled *//* Table Write Protect 02000-02FFF 6L options */#define _WRT_2_OFF_6L 0xFF /* Disabled */#define _WRT_2_ON_6L 0xFB /* Enabled *//* Table Write Protect 03000-03FFF 6L options */#define _WRT_3_OFF_6L 0xFF /* Disabled */#define _WRT_3_ON_6L 0xF7 /* Enabled *//* Data EE Write Protect 6H options */#define _WRTD_OFF_6H 0xFF /* Disabled */#define _WRTD_ON_6H 0x7F /* Enabled *//* Table Write Protect Boot 6H options */#define _WRTB_OFF_6H 0xFF /* Disabled */#define _WRTB_ON_6H 0xBF /* Enabled *//* Config. Write Protect 6H options */#define _WRTC_OFF_6H 0xFF /* Disabled */#define _WRTC_ON_6H 0xDF /* Enabled *//* Table Read Protect 00200-00FFF 7L options */#define _EBTR_0_OFF_7L 0xFF /* Disabled */#define _EBTR_0_ON_7L 0xFE /* Enabled *//* Table Read Protect 01000-01FFF 7L options */#define _EBTR_1_OFF_7L 0xFF /* Disabled */#define _EBTR_1_ON_7L 0xFD /* Enabled *//* Table Read Protect 02000-02FFF 7L options */#define _EBTR_2_OFF_7L 0xFF /* Disabled */#define _EBTR_2_ON_7L 0xFB /* Enabled *//* Table Read Protect 03000-03FFF 7L options */#define _EBTR_3_OFF_7L 0xFF /* Disabled */#define _EBTR_3_ON_7L 0xF7 /* Enabled *//* Table Read Protect Boot 7H options */#define _EBTRB_OFF_7H 0xFF /* Disabled */#define _EBTRB_ON_7H 0xBF /* Enabled *//* Location of User ID words */#define __IDLOC0 0x200000#define __IDLOC1 0x200001#define __IDLOC2 0x200002#define __IDLOC3 0x200003#define __IDLOC4 0x200004#define __IDLOC5 0x200005#define __IDLOC6 0x200006#define __IDLOC7 0x200007#endif // __PIC18F4331__⌨️ 快捷键说明
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