ixparityenacccodelet.c

intel IXP400系列cpu（2.3版）的库文件

/**
 * @file IxParityENAccCodelet.c
 *
 * @author Intel Corporation
 *
 * @date 01 June 2005
 *
 * @brief  Codelet for IXP46X Parity Error Notifier access component.
 *
 * @par
 * IXP400 SW Release version 2.3
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#if defined(__ixp46X)

/********************************************************************* 
 *	user include file 
 *********************************************************************/

#include "IxParityENAccCodelet.h"

/*********************************************************************
 *	private function prototype
 *********************************************************************/

PRIVATE IX_STATUS
ixParityENAccCodeletECCErrorInject (
	BOOL multiBit,	
	BOOL injectLater);

PRIVATE IX_STATUS
ixParityENAccCodeletParityConfigure (IxParityENAccHWParityConfig *pENConfig);

PRIVATE void
ixParityENAccCodeletSDRAMScanTask (void);

PRIVATE IX_STATUS 
ixParityENAccCodeletNewThreadCreate (
	IxOsalVoidFnPtr func, 
	UINT32 priority,
	char *label);

PRIVATE IX_STATUS
ixParityENAccCodeletSDRAMScrub (
	IxParityENAccParityErrorContextMessage *pENContext);

PRIVATE void
ixParityENAccCodeletParityErrActionPerformed (
	IxParityENAccParityErrorContextMessage *pENContext);

PRIVATE void
ixParityENAccCodeletParityErrHandler (void);

#ifdef __vxworks
	PRIVATE void
	ixParityENAccCodeletDataAbortHandler (void);
#endif

PRIVATE void
ixParityENAccCodeletReboot (void);

PRIVATE void 
ixParityENAccCodeletShutDownTask (void);


/*********************************************************************
 *	PRIVATE variable
 *********************************************************************/

PRIVATE BOOL ixParityENAccCodeletTerminate;
PRIVATE UINT32 ixParityENAccCodeletMcuRegBaseAddr = 0;
PRIVATE UINT32 *memAddr4ECCErrorInjection = NULL;
PRIVATE IxOsalSemaphore ixParityENAccCodeletRebootSemId = NULL;
PRIVATE char *ixParityENAccCodeletSourceLabel[] = 
{
    "NPE A IMEM",
    "NPE A DMEM",
    "NPE A External",
    "NPE B IMEM",
    "NPE B DMEM",
    "NPE B External",
    "NPE C IMEM",
    "NPE C DMEM",
    "NPE C External",
    "SWCP",
    "AQM",
    "DDR MCU Single bit",
    "DDR MCU Multi bit",
    "DDR MCU Overflow",
    "PCI Initiator",
    "PCI Target",
    "EBC Chip Select",
    "EBC External Master"
};

PRIVATE char *ixParityENAccCodeletAccessTypeLabel[] =
{
    "READ",
    "WRITE"
};

PRIVATE char *ixParityENAccCodeletRequesterLabel[] =
{
    "Memory Port Interface",
    "North/South AHB Bus"
};

/* 
 * parityENAcc configuration buffer. All components' parity error detection  
 * are set to disable in this buffer.
 */ 
PRIVATE IxParityENAccHWParityConfig ixParityENAccCodeletConfig =
{
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY}, /* NPE-A */ 
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY}, /* NPE-B */
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY}, /* NPE-C */
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,      /* MCU */
     IX_PARITYENACC_DISABLE},
     IX_PARITYENACC_DISABLE,                              /* SWCP */
     IX_PARITYENACC_DISABLE,                              /* AQM */
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE},     /* PBC */    
    {IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,      /* EBC */
     IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
     IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
     IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
     IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY}
};

/*********************************************************************
 *	PUBLIC functions
 *********************************************************************/

PUBLIC IX_STATUS
ixParityENAccCodeletMain (
	BOOL multiBit,		/* 0 - single bit ECC error, 1 - multi bit ECC error */
	BOOL injectNow)		/* 0 - inject ECC error later, 1 - inject ECC error now */
{
	IxParityENAccStatus pENStatus;
	IxParityENAccHWParityConfig pENConfig;

	/* set termination flag to false */
	ixParityENAccCodeletTerminate = FALSE;

#ifdef __vxworks
	/* 
	 * disable data caching. 
	 * If the data is cached, bad ECC generation on SDRAM memory may fail.
	 */
	cacheDisable (DATA_CACHE);
#endif

	/* initialize local parityENAcc configuration buffer */
	memcpy (&pENConfig, &ixParityENAccCodeletConfig, sizeof (IxParityENAccHWParityConfig));

	/* initialize Parity Error Notifier Access Component */
	pENStatus = ixParityENAccInit ();
	if ((IX_PARITYENACC_SUCCESS != pENStatus) && (IX_PARITYENACC_ALREADY_INITIALISED != pENStatus))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: failed to initialize ParityENAcc, error code %d\n",
					pENStatus, 0, 0, 0, 0, 0);
		return IX_FAIL;
	} 

	/* setup callback to handle parity error */
	pENStatus = ixParityENAccCallbackRegister (ixParityENAccCodeletParityErrHandler);
	if (IX_PARITYENACC_SUCCESS != pENStatus)
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: Failed to register parity error callback, error code %d\n",
					pENStatus, 0, 0, 0, 0, 0);
		return IX_FAIL;
	} 

	/* enable MCU parity error detection */
	pENConfig.mcuConfig.singlebitDetectEnabled = IX_PARITYENACC_ENABLE;
	pENConfig.mcuConfig.singlebitCorrectionEnabled = IX_PARITYENACC_ENABLE;
	pENConfig.mcuConfig.multibitDetectionEnabled = IX_PARITYENACC_ENABLE;
	if (IX_SUCCESS != ixParityENAccCodeletParityConfigure (&pENConfig))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: Failed to enable MCU parity error detection\n",
					0, 0, 0, 0, 0, 0);
		return IX_FAIL;
	}    

	if (IX_SUCCESS != ixOsalSemaphoreInit (&ixParityENAccCodeletRebootSemId, 0))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: failed to create semaphore\n",
			0, 0, 0, 0, 0, 0);
		
		return IX_FAIL;
	}

	/* spawn "Shut Down" task */
	if (IX_SUCCESS != 
	    ixParityENAccCodeletNewThreadCreate (ixParityENAccCodeletShutDownTask, 
						 IX_OSAL_MAX_THREAD_PRIORITY, 
						 "Shut Down"))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: failed to start Shut Down thread\n",
					0, 0, 0, 0, 0, 0);

		/* terminate parityENAcc codelet execution */
		ixParityENAccCodeletQuit ();

		return IX_FAIL;
	}

	/* 
	 * connect ixParityENAccCodeletDataAbortHandler() to DATA ABORT exception 
	 * vector, so that ixParityENAccCodeletDataAbortHandler() will be called 
	 * whenever DATA ABORT occurs.
	 */
	#ifdef __vxworks
		excVecSet ((FUNCPTR *)EXC_OFF_DATA, (FUNCPTR)ixParityENAccCodeletDataAbortHandler);
	#endif
 
	ixOsalLog (IX_OSAL_LOG_LVL_DEBUG1, IX_OSAL_LOG_DEV_STDOUT, "ixParityENAccCodeletMain: ParityENAcc is initialized\n", 
				0, 0, 0, 0, 0, 0);

	/* inject ECC error */
	if (IX_SUCCESS != ixParityENAccCodeletECCErrorInject (multiBit, injectNow))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: Failed to inject ECC error\n",
					0, 0, 0, 0, 0, 0);
		/* terminate parityENAcc codelet execution */
		ixParityENAccCodeletQuit ();

		return IX_FAIL;
	}    

	/* start SDRAM memory scan at background */
	if (IX_SUCCESS != 
	    ixParityENAccCodeletNewThreadCreate (ixParityENAccCodeletSDRAMScanTask, 
						 IX_OSAL_DEFAULT_THREAD_PRIORITY,
						 "SDRAM Scan"))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletMain: Failed to start SDRAM memory scan\n",
			0, 0, 0, 0, 0, 0);

		/* terminate parityENAcc codelet execution */
		ixParityENAccCodeletQuit ();

		return IX_FAIL;
	}

	return IX_SUCCESS;

} /* end of ixParityENAccCodeletMain function */


PUBLIC void 
ixParityENAccCodeletQuit ()
{
	IxParityENAccHWParityConfig pENConfig;

	/* set termination flag  */
	ixParityENAccCodeletTerminate = TRUE;

	/* initialize local parityENAcc configuration buffer */
	memcpy (&pENConfig, &ixParityENAccCodeletConfig, sizeof (IxParityENAccHWParityConfig));

	/* disable MCU parity error detection */
	if (IX_SUCCESS != ixParityENAccCodeletParityConfigure (&pENConfig))
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletQuit: Failed to disable MCU parity error detection\n",
			0, 0, 0, 0, 0, 0);
	}    

	/* 
	 * sleep to initiate task switch, so that "SDRAM Scan" thread will
	 * run and quit scanning.
	 */  
	ixOsalSleep (10);

	/* free allocated memory */
	if (NULL != memAddr4ECCErrorInjection)
	{
		IX_OSAL_CACHE_DMA_FREE (memAddr4ECCErrorInjection);

		memAddr4ECCErrorInjection = NULL;
	}

	/* unmap MCU register base address */
	if (0 != ixParityENAccCodeletMcuRegBaseAddr)
	{
		IX_OSAL_MEM_UNMAP (ixParityENAccCodeletMcuRegBaseAddr);

		ixParityENAccCodeletMcuRegBaseAddr = 0;
	}

	/* destroy semaphore */
	if (NULL != ixParityENAccCodeletRebootSemId)
	{
		/* give semaphore to get "Shut Down" thread to quit */
		if (IX_SUCCESS != ixOsalSemaphorePost (&ixParityENAccCodeletRebootSemId))
		{
			ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletQuit: failed to give semaphore\n",
				0, 0, 0, 0, 0, 0);
		}

		/* 
	 	 * sleep to initiate task switch, so that "Shut Down" thread will
	 	 * run and exit. 
	 	 */  
		ixOsalSleep (10);

		if (IX_SUCCESS != ixOsalSemaphoreDestroy (&ixParityENAccCodeletRebootSemId))
		{
			ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccCodeletQuit: failed to destroy semaphore\n",
				0, 0, 0, 0, 0, 0);
		}
		ixParityENAccCodeletRebootSemId = NULL;
	}

#ifdef __vxworks
	/* enable data caching */
	cacheEnable (DATA_CACHE);
#endif

} /* end of ixParityENAccCodeletQuit function */

 
/*********************************************************************
 *	PRIVATE functions
 *********************************************************************/

/**
 * @ingroup IxParityENAccCodelet
 *
 * @fn ixParityENAccCodeletECCErrorInject (
		BOOL multiBit,
		BOOL injectNow)
 *
 * @brief  This function injects ECC error on allocated memory.
 *
 * Memory Controller provides a ECC Test Register (Hex Offset
 * Address = 0xCC00E530) that allows bad ECC generation for ECC
 * testing. To generate bad ECC, first write a 8-bit non-zero
 * value to this test register. This 8-bit non-zero value will
 * be XORed with the ECC generated by subsequent writes, and the
 * computed ECC (bad) will be written to memory. Thus, any 
 * subsequent reads from this memory will result in ECC error.
 * The user needs to provide two parameters to specify how
 * the ECC error should be generated. First, the user has to 
 * specify the type of ECC error injection - single bit or  
 * multi bit. Second, the user has to tell this function when to 
 * cause ECC error after bad ECC generation.
 *	  
 * @param multiBit BOOL [in] - type of ECC error injection.
 *	<LI> FALSE : Single bit ECC error.
 *	<LI> TRUE  : Multi-bit ECC error.
 * 
 * @param injectNow BOOL [in] - preference for when to generate 
 *		ECC error.
 *	<LI> FALSE : This function will only generate bad ECC 
 * 		     on allocated memory. ECC error will only occur
 *		     when the memory is read later.
 *	<LI> TRUE : After generating bad ECC, this function will  
 *		    immediately read the memory to cause ECC error.
 *
 * @return  IX_STATUS
 *          @li IX_SUCCESS - inject bad ECC successfully
 *          @li IX_FAIL    - fails
 */

PRIVATE IX_STATUS
ixParityENAccCodeletECCErrorInject (
	BOOL multiBit,
	BOOL injectNow)
{
	UINT32 *tstECCRegAddr; 

	/* allocate SDRAM memory for ECC error injection */	
	memAddr4ECCErrorInjection = (UINT32 *) IX_OSAL_CACHE_DMA_MALLOC (sizeof (UINT32));