ixhssacccommon_p.h

intel IXP400系列cpu（2.3版）的库文件

/**
 * @file IxHssAccCommon_p.h
 * 
 * @author Intel Corporation
 * @date 10-DEC-2001
 *
 * @brief This file contains the private API of the HSS Access Common
 * module
 *
 * 
 * @par
 * IXP400 SW Release version 2.3
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
*/

/**
 * @defgroup IxHssAccCommon_p IxHssAccCommon_p
 *
 * @brief The private API for the HssAccess Common module
 * 
 * @{
 */

#ifndef IXHSSACCCOMMON_P_H
#define IXHSSACCCOMMON_P_H

#include <stdio.h>
#include "IxHssAcc.h"
#include "IxNpeMh.h"

#include "IxNpeA.h"
#include "IxOsal.h"
/*
 * Global variables
 */
extern IxHssAccHssPort hssPortMax; /**< Number of HSS ports available */

/*
 * Typedefs
 */
 /**
*
* @typedef  IxHssAccNpeBuffer
*
* @brief NPE Shared region structure for hssAcc of IX_OSAL_BUF buffer
*
*/
typedef struct 
{
    UINT32  *ixp_next;      /* Ptr to next buffer */
    UINT16  ixp_len;        /* Buffer length */
    UINT16  ixp_pkt_len;    /* Packet length */
    UINT8   *ixp_data;      /* Ptr to data buffer in SDRAM */
    UINT8   status;
    UINT8   error_count;
    UINT16  reserved0;      /* reserved field */
    UINT32  reserved1;      /* reserved field */
    UINT32  reserved2;      /* reserved field */
    UINT32  reserved3;      /* reserved field */
    UINT32  reserved4;      /* reserved field */

} IxHssAccNpeBuffer;

/**
 * #defines for function return types, etc.
 */

/**
 * @def IX_HSSACC_MAX_CHAN_TIMESLOTS
 *
 * @brief The number of timeslots supported for the channelised
 * service
 */


#ifdef IX_NPE_HSS_MPHY4PORT 
#define IX_HSSACC_MAX_CHAN_TIMESLOTS 16
#else
#define IX_HSSACC_MAX_CHAN_TIMESLOTS 32 
#endif



/**
 * @def IX_HSSACC_BYTES_PER_WORD
 *
 * @brief Number of bytes per word
 */
#define IX_HSSACC_BYTES_PER_WORD 4

/**
 * @def IX_HSSACC_LUT_BITS_PER_TS
 *
 * @brief The number of bits each HSS timeslot consumes in the HSS Co-p LUT
 */
#define IX_HSSACC_LUT_BITS_PER_TS     2

/**
 * @def IX_HSSACC_LUT_BITS_PER_WORD
 *
 * @brief The number of bits per HSS Co-p LUT word entry
 */
#define IX_HSSACC_LUT_BITS_PER_WORD  32

/**
 * @def IX_HSSACC_LUT_WORDS_PER_LUT
 *
 * @brief The total number of words in the HSS Co-p LUT to represent all
 * timeslots with the HSS TDM stream
 */
#define IX_HSSACC_LUT_WORDS_PER_LUT  ((IX_HSSACC_TSLOTS_PER_HSS_PORT * IX_HSSACC_LUT_BITS_PER_TS) / IX_HSSACC_LUT_BITS_PER_WORD)

/**
 * @def IX_HSSACC_SINGLE_HSS_PORT
 *
 * @brief The max number of ports available when only HSS port 0 is 
 * enabled
 */
#define IX_HSSACC_SINGLE_HSS_PORT  IX_HSSACC_HSS_PORT_1

/**
 * @def IX_HSSACC_DUAL_HSS_PORTS
 *
 * @brief The max number of ports available when both HSS ports are 
 * enabled
 */
#define IX_HSSACC_DUAL_HSS_PORTS  IX_HSSACC_HSS_PORT_MAX

/**
 * @def IX_HSSACC_LUT_TS_MASK
 *
 * @brief The mask used to extract HSS timeslot usage from HSS Co-p LUT 
 * word entry
 */
#define IX_HSSACC_LUT_TS_MASK  	     0x00000003

/* ------------------------------------------
   The following are HSS Co-p related defines
   ------------------------------------------ */
/**
 * @def IX_HSSACC_COM_HSSPCR_FTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FTYPE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FTYPE_OFFSET    30

/**
 * @def IX_HSSACC_COM_HSSPCR_FENABLE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FENABLE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FENABLE_OFFSET  28

/**
 * @def IX_HSSACC_COM_HSSPCR_FEDGE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FEDGE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FEDGE_OFFSET    27

/**
 * @def IX_HSSACC_COM_HSSPCR_DEDGE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for DEDGE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_DEDGE_OFFSET    26

/**
 * @def IX_HSSACC_COM_HSSPCR_CLKDIR_OFFSET
 *
 * @brief The HSS co-processor register bit offset for CLKDIR in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_CLKDIR_OFFSET   25

/**
 * @def IX_HSSACC_COM_HSSPCR_FRAME_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FRAME in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FRAME_OFFSET    24

/**
 * @def IX_HSSACC_COM_HSSPCR_HALF_OFFSET
 *
 * @brief The HSS co-processor register bit offset for HALF in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_HALF_OFFSET     21

/**
 * @def IX_HSSACC_COM_HSSPCR_DPOL_OFFSET
 *
 * @brief The HSS co-processor register bit offset for DPOL in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_DPOL_OFFSET     20

/**
 * @def IX_HSSACC_COM_HSSPCR_BITEND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for BITEND in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_BITEND_OFFSET   19

/**
 * @def IX_HSSACC_COM_HSSPCR_ODRAIN_OFFSET
 *
 * @brief The HSS co-processor register bit offset for ODRAIN in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_ODRAIN_OFFSET   18

/**
 * @def IX_HSSACC_COM_HSSPCR_FBIT_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FBIT in
 * HSSTXPCR/HSSRXPCR 
 */
#define IX_HSSACC_COM_HSSPCR_FBIT_OFFSET     17

/**
 * @def IX_HSSACC_COM_HSSPCR_ENABLE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for ENABLE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_ENABLE_OFFSET   16

/**
 * @def IX_HSSACC_COM_HSSPCR_56KTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KTYPE_OFFSET  13

/**
 * @def IX_HSSACC_COM_HSSPCR_UTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for UTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_UTYPE_OFFSET    11

/**
 * @def IX_HSSACC_COM_HSSPCR_FBTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FBTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FBTYPE_OFFSET   10

/**
 * @def IX_HSSACC_COM_HSSPCR_56KEND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KEND in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KEND_OFFSET   9

/**
 * @def IX_HSSACC_COM_HSSPCR_56KSEL_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KSEL in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KSEL_OFFSET   8

/**
 * @def IX_HSSACC_COM_HSSCCR_HFIFO_OFFSET
 *
 * @brief The HSS co-processor register bit offset for HFIFO in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_HFIFO_OFFSET    26

/**
 * @def IX_HSSACC_COM_HSSCCR_LBACK_OFFSET
 *
 * @brief The HSS co-processor register bit offset for LBACK in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_LBACK_OFFSET    25

/**
 * @def IX_HSSACC_COM_HSSCCR_COND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for COND in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_COND_OFFSET     24

/**
 * @def IX_HSSACC_COM_HSSCLKCR_MAIN_OFFSET
 *
 * @brief The HSS co-processor register bit offset for MAIN in HSSCLKCR
 */
#define IX_HSSACC_COM_HSSCLKCR_MAIN_OFFSET   22 

/**
 * @def IX_HSSACC_COM_HSSCLKCR_NUM_OFFSET
 *
 * @brief The HSS co-processor register bit offset for NUM in HSSCLKCR
 */
#define IX_HSSACC_COM_HSSCLKCR_NUM_OFFSET    12

/**
 * @def IX_HSSACC_COM_HSSCLKCR_DENOM_OFFSET
 *
 * @brief The HSS co-processor register bit offset for DENOM in HSSCLKCR
 */
#define IX_HSSACC_COM_HSSCLKCR_DENOM_OFFSET  0
 
/**
 * @def IX_HSSACC_COM_HSSFCR_OFFSET_OFFSET
 *
 * @brief The HSS co-processor register bit offset for OFFSET in HSSFCR
 */
#define IX_HSSACC_COM_HSSFCR_OFFSET_OFFSET   16

/**
 * @def IX_HSSACC_COM_HSSFCR_OFFSET_MAX
 *
 * @brief The HSS co-processor register max value for OFFSET in HSSFCR
 */
#define IX_HSSACC_COM_HSSFCR_OFFSET_MAX   1023

/**
 * @def IX_HSSACC_COM_HSSFCR_SIZE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for SIZE in HSSFCR
 */
#define IX_HSSACC_COM_HSSFCR_SIZE_OFFSET     0

/**
 * @def IX_HSSACC_COM_HSSFCR_SIZE_MAX
 *
 * @brief The HSS co-processor register max value for SIZE in HSSFCR
 */
#define IX_HSSACC_COM_HSSFCR_SIZE_MAX     1023

/**
 * @def IX_HSSACC_IX_NE_SHARED_SHORT_MASK
 *
 * @brief Mask used for sixteen bit (short) values.
 */
 #define IX_HSSACC_IX_NE_SHARED_SHORT_MASK      ((UINT16)0xFFFF)



/**
 * @def IX_HSSACC_ENUM_INVALID
 *
 * @brief Mechanism to validate the upper (MAX) and lower (0) bounds 
 * of a positive enumeration
 *
 * @param int [in] VALUE - the integer value to test
 * @param int [in] MAX - the maximum value to test against
 *
 * This macro returns TRUE if the bounds are invalid and FALSE if
 * they are okay. NOTE: MAX will be an invalid value, so check >=
 *
 * @return none
 */
#define IX_HSSACC_ENUM_INVALID(VALUE, MAX) ((((VALUE) < 0) || ((VALUE) >= (MAX))) ? TRUE : FALSE)



/**
 * @def IX_HSSACC_PKT_MMU_PHY_TO_VIRT
 *
 * @brief HssAccess abstraction to the real macro in IxOsal.h
 *
 * @param UINT32 * [in] addr - address to operate on
 *
 * This macro converts a physical address to a virtual one 
 *
 * @return UINT32 *
 */
#define IX_HSSACC_PKT_MMU_PHY_TO_VIRT(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)

/**
 * @def IX_HSSACC_PKT_MMU_VIRT_TO_PHY
 *
 * @brief HssAccess abstraction to the real macro in IxOsal.h
 *
 * @param UINT32 * [in] addr - address to operate on
 *
 * This macro converts a virtual address to a physical one 
 *
 * @return UINT32 *
 */
#define IX_HSSACC_PKT_MMU_VIRT_TO_PHY(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)


/**
 * @def IX_HSSACC_IX_NE_SHARED(bufPtr)
 *
 * @brief Macro to extract the NPE shared region address 
 * from address of the OS dependant region of IX_OSAL_BUF buffer
 *
 * @param int [in] bufPtr - The address of the OS dependant region 
 * of IX_OSAL_BUF buffer
 *
 * @return (IxHssAccNpeBuffer *) - Pointer to the NPE shared region 
 * of IX_OSAL_BUF buffer.
 */
#define IX_HSSACC_IX_NE_SHARED(bufPtr) \
    ((IxHssAccNpeBuffer *)&((bufPtr)->ix_ne))

/**
 * @def IX_HSSACC_IX_OSAL_MBUF_FROM_IX_NE(ix_ne_ptr)
 *
 * @brief Macro to extract the OS dependant region address 
 * from the address of the NPE shared region of IX_OSAL_BUF buffer
 *
 * @param int [in] ix_ne_ptr - the address of the NPE shared region 
 * of IX_OSAL_BUF buffer
 *
 * @return (IX_OSAL_MBUF *) - Pointer to the OS dependant region
 * of IX_OSAL_BUF buffer.
 */
#define IX_HSSACC_IX_OSAL_MBUF_FROM_IX_NE(ix_ne_ptr) \
    ((IX_OSAL_MBUF *)((UINT8 *)(ix_ne_ptr) - offsetof(IX_OSAL_MBUF, ix_ne)))

/**
 * @def IX_HSSACC_IX_NE_SHARED_NEXT(bufPtr)
 *
 * @brief Macro to extract the pointer to the NPE shared region of  
 * the next IX_OSAL_BUF buffer in the chain from the address of the
 * IX_OSAL_BUF buffer
 *
 * @param int [in] bufPtr - the address of the IX_OSAL_BUF buffer
 *
 * @return (UINT32 *) - Pointer to the NPE shared region of the next
 * IX_OSAL_BUF buffer in the chain.
 */
#define IX_HSSACC_IX_NE_SHARED_NEXT(bufPtr) \
    IX_HSSACC_IX_NE_SHARED(bufPtr)->ixp_next

/**
 * @def IX_HSSACC_IX_NE_SHARED_LEN(bufPtr)
 *
 * @brief Macro to extract the length of the buffer from the address
 * of the IX_OSAL_BUF buffer. 
 *
 * @param int [in] bufPtr - the address of the IX_OSAL_BUF buffer
 *
 * @return UINT16  - Length of the IX_OSAL_BUF buffer
 */
#define IX_HSSACC_IX_NE_SHARED_LEN(bufPtr) \
    IX_HSSACC_IX_NE_SHARED(bufPtr)->ixp_len

/**