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Atmel AT91SAM7S Interrupt example code

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<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="TWI_MREAD"></a><b>TWI_MREAD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_MREAD">AT91C_TWI_MREAD</a></font></td><td><b>Master Read Direction</b><br>0: Master write direction<br>1: Master read direction</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..16</td><td align="CENTER"><a name="TWI_DADR"></a><b>TWI_DADR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_DADR">AT91C_TWI_DADR</a></font></td><td><b>Device Address</b><br>The device address is used in master mode to access slave devices in read or write mode.</td></tr>
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<a name="TWI_IADR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_IADR  <i>Internal Address Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_IADR">AT91C_TWI_IADR</a></i> 0xFFFB800C</font></null></ul><br>0, 1, 2 or 3 bytes depending on IADRSZ<a name="TWI_CWGR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_CWGR  <i>Clock Waveform Generator Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_CWGR">AT91C_TWI_CWGR</a></i> 0xFFFB8010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="TWI_CLDIV"></a><b>TWI_CLDIV</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_CLDIV">AT91C_TWI_CLDIV</a></font></td><td><b>Clock Low Divider</b><br>The SCL low period is defined as follows: Tlow = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="TWI_CHDIV"></a><b>TWI_CHDIV</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_CHDIV">AT91C_TWI_CHDIV</a></font></td><td><b>Clock High Divider</b><br>The SCL high period is defined as follows: Thigh = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18..16</td><td align="CENTER"><a name="TWI_CKDIV"></a><b>TWI_CKDIV</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_CKDIV">AT91C_TWI_CKDIV</a></font></td><td><b>Clock Divider</b><br>The CKDIV is used to increase both SCL high and low periods.</td></tr>
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<a name="TWI_SR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_SR">AT91C_TWI_SR</a></i> 0xFFFB8020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
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<a name="TWI_IER"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_IER">AT91C_TWI_IER</a></i> 0xFFFB8024</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
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<a name="TWI_IDR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_IDR">AT91C_TWI_IDR</a></i> 0xFFFB8028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
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<a name="TWI_IMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_IMR">AT91C_TWI_IMR</a></i> 0xFFFB802C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_TXCOMP"></a><b>TWI_TXCOMP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXCOMP">AT91C_TWI_TXCOMP</a></font></td><td><b>Transmission Completed</b><br>0: In master, during the length of the current frame. In slave, from START received to STOP received.<br>1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in theTWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_TXRDY"></a><b>TWI_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_TXRDY">AT91C_TWI_TXRDY</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.<br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error</b><br>0: TWI_RHR has not been loaded while RXRDY was set<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_UNRE"></a><b>TWI_UNRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_UNRE">AT91C_TWI_UNRE</a></font></td><td><b>Underrun Error</b><br>0: No underrun error<br>1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="TWI_NACK"></a><b>TWI_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_TWI_NACK">AT91C_TWI_NACK</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.</td></tr>
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<a name="TWI_RHR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_RHR  <i>Receive Holding Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_RHR">AT91C_TWI_RHR</a></i> 0xFFFB8030</font></null></ul><br>Master or Slave Receive Holding Data<a name="TWI_THR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> TWI_THR  <i>Transmit Holding Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7S256_h.html#AT91C_TWI_THR">AT91C_TWI_THR</a></i> 0xFFFB8034</font></null></ul><br>Master or Slave Transmit Holding Data</null><hr></html>