fpga_led_test.fit.rpt

FPGA开发板上自带的LED测试例程

; Differential LVPECL              ; 0 pF  ; 100 Ohm (Differential)             ;
+----------------------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |FPGA_led_test             ; 0 (0)       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 2    ; 0            ; |FPGA_led_test      ;
+----------------------------+-------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------+
; Delay Chain Summary                                                           ;
+------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+------+----------+---------------+---------------+-----------------------+-----+
; key1 ; Input    ; 6             ; 6             ; --                    ; --  ;
; led1 ; Output   ; --            ; --            ; --                    ; --  ;
+------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; key1                ;                   ;         ;
;      - led1         ; 1                 ; 6       ;
+---------------------+-------------------+---------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+------+--------------------------+
; Name ; Fan-Out                  ;
+------+--------------------------+
; key1 ; 1                        ;
+------+--------------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; Block interconnects        ; 1 / 15,666 ( < 1 % ) ;
; C16 interconnects          ; 1 / 812 ( < 1 % )    ;
; C4 interconnects           ; 0 / 11,424 ( 0 % )   ;
; Direct links               ; 0 / 15,666 ( 0 % )   ;
; Global clocks              ; 0 / 8 ( 0 % )        ;
; Local interconnects        ; 0 / 4,608 ( 0 % )    ;
; R24 interconnects          ; 1 / 652 ( < 1 % )    ;
; R4 interconnects           ; 1 / 13,328 ( < 1 % ) ;
+----------------------------+----------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 22 12:55:11 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FPGA_led_test -c FPGA_led_test
Info: Selected device EP2C5Q208C8 for design "FPGA_led_test"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5Q208I8 is compatible
    Info: Device EP2C8Q208C8 is compatible
    Info: Device EP2C8Q208I8 is compatible
Info: Starting register packing
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Timing characteristics of device EP2C5Q208C8 are preliminary
Warning: Found 1 output pins without output pin load capacitance assignment
    Warning: Pin "led1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Processing ended: Sat Apr 22 12:55:16 2006
    Info: Elapsed time: 00:00:06