📄 msp430x14x.h
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#define RXERR 0x01
/************************************************************
* UART 0/1
************************************************************/
#define U0CTL_ 0x0070 /* UART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ 0x0072 /* UART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb U0BR0 = U0BR0_;
#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb U0BR1 = U0BR1_;
#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */
const sfrb U0RXBUF = U0RXBUF_;
#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */
sfrb U0TXBUF = U0TXBUF_;
#define U1CTL_ 0x0078 /* UART 1 Control */
sfrb U1CTL = U1CTL_;
#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */
sfrb U1TCTL = U1TCTL_;
#define U1RCTL_ 0x007A /* UART 1 Receive Control */
sfrb U1RCTL = U1RCTL_;
#define U1MCTL_ 0x007B /* UART 1 Modulation Control */
sfrb U1MCTL = U1MCTL_;
#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */
sfrb U1BR0 = U1BR0_;
#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb U1BR1 = U1BR1_;
#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */
const sfrb U1RXBUF = U1RXBUF_;
#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */
sfrb U1TXBUF = U1TXBUF_;
/* Alternate register names */
#define UCTL0_ 0x0070 /* UART 0 Control */
sfrb UCTL0 = UCTL0_;
#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL0 = UTCTL0_;
#define URCTL0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL0 = URCTL0_;
#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL0 = UMCTL0_;
#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR00 = UBR00_;
#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR10 = UBR10_;
#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF0 = RXBUF0_;
#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF0 = TXBUF0_;
#define UCTL1_ 0x0078 /* UART 1 Control */
sfrb UCTL1 = UCTL1_;
#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL1 = UTCTL1_;
#define URCTL1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL1 = URCTL1_;
#define UMCTL1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL1 = UMCTL1_;
#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR01 = UBR01_;
#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR11 = UBR11_;
#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF1 = RXBUF1_;
#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF1 = TXBUF1_;
#define UCTL_0_ 0x0070 /* UART 0 Control */
sfrb UCTL_0 = UCTL_0_;
#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL_0 = UTCTL_0_;
#define URCTL_0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL_0 = URCTL_0_;
#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL_0 = UMCTL_0_;
#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR0_0 = UBR0_0_;
#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR1_0 = UBR1_0_;
#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF_0 = RXBUF_0_;
#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF_0 = TXBUF_0_;
#define UCTL_1_ 0x0078 /* UART 1 Control */
sfrb UCTL_1 = UCTL_1_;
#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL_1 = UTCTL_1_;
#define URCTL_1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL_1 = URCTL_1_;
#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL_1 = UMCTL_1_;
#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR0_1 = UBR0_1_;
#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR1_1 = UBR1_1_;
#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF_1 = RXBUF_1_;
#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF_1 = TXBUF_1_;
/************************************************************
* Timer A
************************************************************/
#define TAIV_ 0x012E /* Timer A Interrupt Vector Word */
sfrw TAIV = TAIV_;
#define TACTL_ 0x0160 /* Timer A Control */
sfrw TACTL = TACTL_;
#define CCTL0_ 0x0162 /* Timer A Capture/Compare Control 0 */
sfrw CCTL0 = CCTL0_;
#define CCTL1_ 0x0164 /* Timer A Capture/Compare Control 1 */
sfrw CCTL1 = CCTL1_;
#define CCTL2_ 0x0166 /* Timer A Capture/Compare Control 2 */
sfrw CCTL2 = CCTL2_;
#define TAR_ 0x0170 /* Timer A */
sfrw TAR = TAR_;
#define CCR0_ 0x0172 /* Timer A Capture/Compare 0 */
sfrw CCR0 = CCR0_;
#define CCR1_ 0x0174 /* Timer A Capture/Compare 1 */
sfrw CCR1 = CCR1_;
#define CCR2_ 0x0176 /* Timer A Capture/Compare 2 */
sfrw CCR2 = CCR2_;
#define TASSEL2 0x0400 /* to distinguish from UART SSELx */
#define TASSEL1 0x0200
#define TASSEL0 0x0100
#define ID1 0x0080
#define ID0 0x0040
#define MC1 0x0020
#define MC0 0x0010
#define TACLR 0x0004
#define TAIE 0x0002
#define TAIFG 0x0001
#define MC_0 00*0x10
#define MC_1 01*0x10
#define MC_2 02*0x10
#define MC_3 03*0x10
#define ID_0 00*0x40
#define ID_1 01*0x40
#define ID_2 02*0x40
#define ID_3 03*0x40
#define TASSEL_0 00*0x100
#define TASSEL_1 01*0x100
#define TASSEL_2 02*0x100
#define TASSEL_3 03*0x100
#define CM1 0x8000
#define CM0 0x4000
#define CCIS1 0x2000
#define CCIS0 0x1000
#define SCS 0x0800
#define SCCI 0x0400
#define CAP 0x0100
#define OUTMOD2 0x0080
#define OUTMOD1 0x0040
#define OUTMOD0 0x0020
#define CCIE 0x0010
#define CCI 0x0008
#define OUT 0x0004
#define COV 0x0002
#define CCIFG 0x0001
#define OUTMOD_0 00*0x20
#define OUTMOD_1 01*0x20
#define OUTMOD_2 02*0x20
#define OUTMOD_3 03*0x20
#define OUTMOD_4 04*0x20
#define OUTMOD_5 05*0x20
#define OUTMOD_6 06*0x20
#define OUTMOD_7 07*0x20
#define CCIS_0 00*0x1000
#define CCIS_1 01*0x1000
#define CCIS_2 02*0x1000
#define CCIS_3 03*0x1000
#define CM_0 00*0x4000
#define CM_1 01*0x4000
#define CM_2 02*0x4000
#define CM_3 03*0x4000
/************************************************************
* Timer B
************************************************************/
#define TBIV_ 0x011E /* Timer B Interrupt Vector Word */
sfrw TBIV = TBIV_;
#define TBCTL_ 0x0180 /* Timer B Control */
sfrw TBCTL = TBCTL_;
#define TBCCTL0_ 0x0182 /* Timer B Capture/Compare Control 0 */
sfrw TBCCTL0 = TBCCTL0_;
#define TBCCTL1_ 0x0184 /* Timer B Capture/Compare Control 1 */
sfrw TBCCTL1 = TBCCTL1_;
#define TBCCTL2_ 0x0186 /* Timer B Capture/Compare Control 2 */
sfrw TBCCTL2 = TBCCTL2_;
#define TBCCTL3_ 0x0188 /* Timer B Capture/Compare Control 3 */
sfrw TBCCTL3 = TBCCTL3_;
#define TBCCTL4_ 0x018A /* Timer B Capture/Compare Control 4 */
sfrw TBCCTL4 = TBCCTL4_;
#define TBCCTL5_ 0x018C /* Timer B Capture/Compare Control 5 */
sfrw TBCCTL5 = TBCCTL5_;
#define TBCCTL6_ 0x018E /* Timer B Capture/Compare Control 6 */
sfrw TBCCTL6 = TBCCTL6_;
#define TBR_ 0x0190 /* Timer B */
sfrw TBR = TBR_;
#define TBCCR0_ 0x0192 /* Timer B Capture/Compare 0 */
sfrw TBCCR0 = TBCCR0_;
#define TBCCR1_ 0x0194 /* Timer B Capture/Compare 1 */
sfrw TBCCR1 = TBCCR1_;
#define TBCCR2_ 0x0196 /* Timer B Capture/Compare 2 */
sfrw TBCCR2 = TBCCR2_;
#define TBCCR3_ 0x0198 /* Timer B Capture/Compare 3 */
sfrw TBCCR3 = TBCCR3_;
#define TBCCR4_ 0x019A /* Timer B Capture/Compare 4 */
sfrw TBCCR4 = TBCCR4_;
#define TBCCR5_ 0x019C /* Timer B Capture/Compare 5 */
sfrw TBCCR5 = TBCCR5_;
#define TBCCR6_ 0x019E /* Timer B Capture/Compare 6 */
sfrw TBCCR6 = TBCCR6_;
#define SHR1 0x4000
#define SHR0 0x2000
#define CNTL1 0x1000
#define CNTL0 0x0800
#define TBSSEL2 0x0400
#define TBSSEL1 0x0200
#define TBSSEL0 0x0100
#define TBCLR 0x0004
#define TBIE 0x0002
#define TBIFG 0x0001
#define TBSSEL_0 00*0x0100
#define TBSSEL_1 01*0x0100
#define TBSSEL_2 02*0x0100
#define TBSSEL_3 03*0x0100
#define CNTL_0 00*0x0800
#define CNTL_1 01*0x0800
#define CNTL_2 02*0x0800
#define CNTL_3 03*0x0800
#define SHR_0 00*0x2000
#define SHR_1 01*0x2000
#define SHR_2 02*0x2000
#define SHR_3 03*0x2000
#define SLSHR1 0x0400
#define SLSHR0 0x0200
#define SLSHR_0 00*0x0200
#define SLSHR_1 01*0x0200
#define SLSHR_2 02*0x0200
#define SLSHR_3 03*0x0200
/************************************************************
* Basic Clock Module
************************************************************/
#define DCOCTL_ 0x0056 /* DCO Clock Frequency Control */
sfrb DCOCTL = DCOCTL_;
#define BCSCTL1_ 0x0057 /* Basic Clock System Control 1 */
sfrb BCSCTL1 = BCSCTL1_;
#define BCSCTL2_ 0x0058 /* Basic Clock System Control 2 */
sfrb BCSCTL2 = BCSCTL2_;
#define MOD0 0x01
#define MOD1 0x02
#define MOD2 0x04
#define MOD3 0x08
#define MOD4 0x10
#define DCO0 0x20
#define DCO1 0x40
#define DCO2 0x80
#define RSEL0 0x01
#define RSEL1 0x02
#define RSEL2 0x04
#define XT5V 0x08
#define DIVA0 0x10
#define DIVA1 0x20
#define XTS 0x40
#define XTOFF 0x80
#define DCOR 0x01
#define DIVS0 0x02
#define DIVS1 0x04
#define SELS 0x08
#define DIVM0 0x10
#define DIVM1 0x20
#define SELM0 0x40
#define SELM1 0x80
/*************************************************************
* Flash Memory
*************************************************************/
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