📄 buf2440.rpt
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nEXTBUS = LCELL( _EQ009 $ GND);
_EQ009 = nFRE & nFWE & nGCS0 & nGCS1 & nGCS2 & nGCS3 & nGCS4 &
nGCS5 & nGCS6;
-- Node name is 'nWAIT_OD'
-- Equation name is 'nWAIT_OD', location is LC006, type is output.
nWAIT_OD = OPNDRN(_LC006);
_LC006 = LCELL( _EQ010 $ VCC);
_EQ010 = !_LC005 & !nGCS4 & _X001;
_X001 = EXP(!_LC002 & !_LC008);
-- Node name is '|DMATEST:m0|:205' = '|DMATEST:m0|counter0'
-- Equation name is '_LC017', type is buried
_LC017 = TFFE( _EQ011, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ011 = _LC017 & !_LC024 & !_LC025 & _LC027 & !_LC029
# _LC017 & _LC024 & !_LC025 & !_LC027 & !_LC029
# !_LC017 & !_LC024 & _LC027 & !_LC029;
-- Node name is '|DMATEST:m0|:204' = '|DMATEST:m0|counter1'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _EQ012, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ012 = !_LC017 & !_LC020 & !_LC024 & !_LC025 & _LC027 & !_LC029
# _LC020 & !_LC024 & _LC025 & _LC027 & !_LC029
# !_LC017 & _LC020 & !_LC024 & _LC027 & !_LC029
# _LC020 & _LC024 & !_LC025 & !_LC027 & !_LC029;
-- Node name is '|DMATEST:m0|:203' = '|DMATEST:m0|counter2'
-- Equation name is '_LC030', type is buried
_LC030 = TFFE( _EQ013, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ013 = !_LC017 & !_LC020 & !_LC024 & !_LC025 & _LC027 & !_LC029 &
!_LC030
# !_LC017 & !_LC020 & !_LC024 & _LC027 & !_LC029 & _LC030
# !_LC024 & _LC025 & _LC027 & !_LC029 & _LC030
# _LC024 & !_LC025 & !_LC027 & !_LC029 & _LC030;
-- Node name is '|DMATEST:m0|:202' = '|DMATEST:m0|counter3'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( _EQ014, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ014 = !_LC017 & !_LC022 & !_LC024 & !_LC025 & _LC027 & !_LC028 &
!_LC029
# !_LC017 & _LC022 & !_LC024 & _LC027 & !_LC028 & !_LC029
# _LC022 & !_LC024 & _LC025 & _LC027 & !_LC029
# _LC022 & _LC024 & !_LC025 & !_LC027 & !_LC029;
-- Node name is '|DMATEST:m0|lpm_add_sub:308|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ015 $ _LC030);
_EQ015 = _LC020 & !_LC030;
-- Node name is '|DMATEST:m0|:77' = '|DMATEST:m0|snDACK'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( nDACK $ GND, GLOBAL( clock), VCC, VCC, VCC);
-- Node name is '|DMATEST:m0|:20' = '|DMATEST:m0|snDmaStart'
-- Equation name is '_LC021', type is buried
_LC021 = DFFE( nDmaStart $ GND, GLOBAL( clock), VCC, VCC, VCC);
-- Node name is '|DMATEST:m0|:294'
-- Equation name is '_LC029', type is buried
_LC029 = TFFE( GND, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
-- Node name is '|DMATEST:m0|:295'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _EQ016 $ GND, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ016 = !_LC017 & !_LC020 & !_LC022 & _LC024 & !_LC025 & _LC027 &
!_LC029 & !_LC030 & !nDmaStart
# !dmaMode0 & dmaMode1 & !_LC021 & !_LC024 & !_LC025 & !_LC027 &
!_LC029
# _LC024 & _LC025 & !_LC027 & !_LC029 & _LC031
# _LC024 & _LC025 & _LC027 & !_LC029
# !_LC024 & !_LC025 & _LC027 & !_LC029;
-- Node name is '|DMATEST:m0|:296'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _EQ017 $ VCC, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ017 = !_LC017 & !_LC020 & !_LC022 & !_LC025 & _LC027 & !_LC030
# _LC024 & _LC025 & !_LC027 & _LC031
# !_LC024 & !_LC025 & _X002
# _LC029;
_X002 = EXP(!dmaMode0 & dmaMode1 & !_LC021 & !_LC027);
-- Node name is '|DMATEST:m0|:297'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _EQ018 $ VCC, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ018 = _LC025 & !_LC027 & !_LC029 & _LC031
# !_LC024 & _LC025 & _LC027 & !_LC029
# _LC024 & !_LC025 & !_LC029 & _X003
# !_LC024 & !_LC025 & !_LC027 & _LC029
# !_LC025 & !_LC027 & !_LC029 & _X004;
_X003 = EXP(!_LC017 & !_LC020 & !_LC022 & _LC027 & !_LC030 & !nDmaStart);
_X004 = EXP( dmaMode0 & !dmaMode1 & !_LC021);
-- Node name is '|WAITTEST:w0|:93' = '|WAITTEST:w0|counter0'
-- Equation name is '_LC007', type is buried
_LC007 = TFFE( _EQ019, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ019 = !_LC005 & _LC007 & _LC008
# _LC002 & !_LC005;
-- Node name is '|WAITTEST:w0|:92' = '|WAITTEST:w0|counter1'
-- Equation name is '_LC004', type is buried
_LC004 = TFFE( _EQ020, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ020 = !_LC002 & _LC004 & !_LC005 & _LC008
# _LC002 & !_LC005 & !_LC007;
-- Node name is '|WAITTEST:w0|:91' = '|WAITTEST:w0|counter2'
-- Equation name is '_LC013', type is buried
_LC013 = TFFE( _EQ021, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ021 = !_LC002 & !_LC005 & _LC008 & _LC013
# _LC002 & !_LC004 & !_LC005 & !_LC007;
-- Node name is '|WAITTEST:w0|:90' = '|WAITTEST:w0|counter3'
-- Equation name is '_LC012', type is buried
_LC012 = TFFE( _EQ022, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ022 = !_LC002 & !_LC005 & _LC008 & _LC012
# _LC002 & !_LC005 & !_LC007 & !_LC010;
-- Node name is '|WAITTEST:w0|lpm_add_sub:249|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC010', type is buried
_LC010 = LCELL( _EQ023 $ _LC013);
_EQ023 = _LC004 & !_LC013;
-- Node name is '|WAITTEST:w0|:210' = '|WAITTEST:w0|wState0'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _EQ024 $ _LC002, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ024 = _LC002 & !_LC004 & !_LC005 & !_LC007 & _LC008 & !_LC012 &
!_LC013
# !_LC002 & _LC005 & _LC008 & !nOE
# !_LC002 & !_LC005 & !_LC008 & !nGCS4
# _LC005 & !_LC008;
-- Node name is '|WAITTEST:w0|:209' = '|WAITTEST:w0|wState1'
-- Equation name is '_LC002', type is buried
_LC002 = TFFE( _EQ025, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ025 = _LC002 & !_LC004 & !_LC005 & !_LC007 & _LC008 & !_LC012 &
!_LC013
# !_LC002 & _LC005 & _LC008 & !nGCS4 & nOE
# _LC002 & _LC005 & !_LC008 & nGCS4
# !_LC002 & !_LC005 & _LC008;
-- Node name is '|WAITTEST:w0|:208' = '|WAITTEST:w0|wState2'
-- Equation name is '_LC005', type is buried
_LC005 = TFFE( _EQ026, GLOBAL( clock), GLOBAL( nReset), VCC, VCC);
_EQ026 = _LC002 & !_LC004 & !_LC005 & !_LC007 & _LC008 & !_LC012 &
!_LC013
# !_LC002 & _LC005 & _LC008 & nGCS4 & nOE
# _LC002 & _LC005 & !_LC008 & nGCS4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\work\2440\sw\2440_buffer\buf2440.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000AE' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,403K
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