📄 buf2440.rpt
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** OUTPUTS **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
6 3 A OUTPUT t 0 0 0 2 0 0 0 BUFDIR
16 11 A OUTPUT t 0 0 0 2 0 0 0 BUFDIR1
39 19 B TRI t 0 0 0 0 2 0 0 data0
40 18 B TRI t 0 0 0 0 2 0 0 data1
34 23 B TRI t 0 0 0 0 2 0 0 data2
31 26 B TRI t 0 0 0 0 2 0 0 data3
24 32 B OUTPUT t 0 0 0 0 4 0 0 nDREQ
19 14 A OUTPUT t 0 0 0 9 0 0 0 nEXTBUS
9 6 A OPNDRN t 1 0 0 1 3 0 0 nWAIT_OD
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\work\2440\sw\2440_buffer\buf2440.rpt
buf2440
** BURIED LOGIC **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(4) 1 A SOFT s t 0 0 0 2 0 0 0 data3~1
(28) 28 B SOFT t 0 0 0 0 2 0 1 |DMATEST:m0|lpm_add_sub:308|addcore:adder|addcore:adder0|gcp2
(37) 21 B DFFE + t 0 0 0 1 0 0 3 |DMATEST:m0|snDmaStart (|DMATEST:m0|:20)
(25) 31 B DFFE + t 0 0 0 1 0 0 3 |DMATEST:m0|snDACK (|DMATEST:m0|:77)
(36) 22 B TFFE + t 0 0 0 0 7 0 4 |DMATEST:m0|counter3 (|DMATEST:m0|:202)
(26) 30 B TFFE + t 0 0 0 0 7 0 5 |DMATEST:m0|counter2 (|DMATEST:m0|:203)
(38) 20 B TFFE + t 0 0 0 0 6 0 6 |DMATEST:m0|counter1 (|DMATEST:m0|:204)
(41) 17 B TFFE + t 0 0 0 0 5 0 7 |DMATEST:m0|counter0 (|DMATEST:m0|:205)
(27) 29 B TFFE + t 0 0 0 0 0 1 7 |DMATEST:m0|:294
(29) 27 B DFFE + t 1 0 1 3 10 1 7 |DMATEST:m0|:295
(32) 25 B DFFE + t 1 0 0 2 10 1 7 |DMATEST:m0|:296
(33) 24 B DFFE + t 3 0 1 3 10 1 7 |DMATEST:m0|:297
(14) 10 A SOFT t 0 0 0 0 2 0 1 |WAITTEST:w0|lpm_add_sub:249|addcore:adder|addcore:adder0|gcp2
(17) 12 A TFFE + t 0 0 0 0 6 0 4 |WAITTEST:w0|counter3 (|WAITTEST:w0|:90)
(18) 13 A TFFE + t 0 0 0 0 6 0 5 |WAITTEST:w0|counter2 (|WAITTEST:w0|:91)
(7) 4 A TFFE + t 0 0 0 0 5 0 6 |WAITTEST:w0|counter1 (|WAITTEST:w0|:92)
(11) 7 A TFFE + t 0 0 0 0 4 0 7 |WAITTEST:w0|counter0 (|WAITTEST:w0|:93)
(8) 5 A TFFE + t 0 0 0 2 7 5 7 |WAITTEST:w0|wState2 (|WAITTEST:w0|:208)
(5) 2 A TFFE + t 0 0 0 2 7 5 7 |WAITTEST:w0|wState1 (|WAITTEST:w0|:209)
(12) 8 A DFFE + t 1 0 1 2 7 1 7 |WAITTEST:w0|wState0 (|WAITTEST:w0|:210)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\work\2440\sw\2440_buffer\buf2440.rpt
buf2440
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------- LC3 BUFDIR
| +----------------------- LC11 BUFDIR1
| | +--------------------- LC1 data3~1
| | | +------------------- LC14 nEXTBUS
| | | | +----------------- LC6 nWAIT_OD
| | | | | +--------------- LC10 |WAITTEST:w0|lpm_add_sub:249|addcore:adder|addcore:adder0|gcp2
| | | | | | +------------- LC12 |WAITTEST:w0|counter3
| | | | | | | +----------- LC13 |WAITTEST:w0|counter2
| | | | | | | | +--------- LC4 |WAITTEST:w0|counter1
| | | | | | | | | +------- LC7 |WAITTEST:w0|counter0
| | | | | | | | | | +----- LC5 |WAITTEST:w0|wState2
| | | | | | | | | | | +--- LC2 |WAITTEST:w0|wState1
| | | | | | | | | | | | +- LC8 |WAITTEST:w0|wState0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC10 -> - - - - - - * - - - - - - | * - | <-- |WAITTEST:w0|lpm_add_sub:249|addcore:adder|addcore:adder0|gcp2
LC12 -> - - - - - - * - - - * * * | * - | <-- |WAITTEST:w0|counter3
LC13 -> - - - - - * - * - - * * * | * - | <-- |WAITTEST:w0|counter2
LC4 -> - - - - - * - * * - * * * | * - | <-- |WAITTEST:w0|counter1
LC7 -> - - - - - - * * * * * * * | * - | <-- |WAITTEST:w0|counter0
LC5 -> - - - - * - * * * * * * * | * * | <-- |WAITTEST:w0|wState2
LC2 -> - - - - * - * * * * * * * | * * | <-- |WAITTEST:w0|wState1
LC8 -> - - - - * - * * * * * * * | * - | <-- |WAITTEST:w0|wState0
Pin
43 -> - - - - - - - - - - - - - | - - | <-- clock
11 -> * * - * - - - - - - - - - | * - | <-- nFRE
12 -> - - - * - - - - - - - - - | * - | <-- nFWE
14 -> - - - * - - - - - - - - - | * - | <-- nGCS0
36 -> - - - * - - - - - - - - - | * - | <-- nGCS1
17 -> - - - * - - - - - - - - - | * - | <-- nGCS2
4 -> - - - * - - - - - - - - - | * - | <-- nGCS3
5 -> - - * * * - - - - - * * * | * - | <-- nGCS4
41 -> - - - * - - - - - - - - - | * - | <-- nGCS5
33 -> - - - * - - - - - - - - - | * - | <-- nGCS6
18 -> * * * - - - - - - - * * * | * - | <-- nOE
1 -> - - - - - - - - - - - - - | - - | <-- nReset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\work\2440\sw\2440_buffer\buf2440.rpt
buf2440
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC19 data0
| +----------------------------- LC18 data1
| | +--------------------------- LC23 data2
| | | +------------------------- LC26 data3
| | | | +----------------------- LC28 |DMATEST:m0|lpm_add_sub:308|addcore:adder|addcore:adder0|gcp2
| | | | | +--------------------- LC21 |DMATEST:m0|snDmaStart
| | | | | | +------------------- LC31 |DMATEST:m0|snDACK
| | | | | | | +----------------- LC22 |DMATEST:m0|counter3
| | | | | | | | +--------------- LC30 |DMATEST:m0|counter2
| | | | | | | | | +------------- LC20 |DMATEST:m0|counter1
| | | | | | | | | | +----------- LC17 |DMATEST:m0|counter0
| | | | | | | | | | | +--------- LC29 |DMATEST:m0|:294
| | | | | | | | | | | | +------- LC27 |DMATEST:m0|:295
| | | | | | | | | | | | | +----- LC25 |DMATEST:m0|:296
| | | | | | | | | | | | | | +--- LC24 |DMATEST:m0|:297
| | | | | | | | | | | | | | | +- LC32 nDREQ
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC28 -> - - - - - - - * - - - - - - - - | - * | <-- |DMATEST:m0|lpm_add_sub:308|addcore:adder|addcore:adder0|gcp2
LC21 -> - - - - - - - - - - - - * * * - | - * | <-- |DMATEST:m0|snDmaStart
LC31 -> - - - - - - - - - - - - * * * - | - * | <-- |DMATEST:m0|snDACK
LC22 -> - - - - - - - * - - - - * * * - | - * | <-- |DMATEST:m0|counter3
LC30 -> - - - - * - - - * - - - * * * - | - * | <-- |DMATEST:m0|counter2
LC20 -> - - - - * - - - * * - - * * * - | - * | <-- |DMATEST:m0|counter1
LC17 -> - - - - - - - * * * * - * * * - | - * | <-- |DMATEST:m0|counter0
LC29 -> - - - - - - - * * * * * * * * * | - * | <-- |DMATEST:m0|:294
LC27 -> - - - - - - - * * * * - * * * * | - * | <-- |DMATEST:m0|:295
LC25 -> - - - - - - - * * * * - * * * * | - * | <-- |DMATEST:m0|:296
LC24 -> - - - - - - - * * * * - * * * * | - * | <-- |DMATEST:m0|:297
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clock
20 -> - - - - - - - - - - - - * * * - | - * | <-- dmaMode0
21 -> - - - - - - - - - - - - * * * - | - * | <-- dmaMode1
8 -> - - - - - - * - - - - - - - - - | - * | <-- nDACK
37 -> - - - - - * - - - - - - * - * - | - * | <-- nDmaStart
1 -> - - - - - - - - - - - - - - - - | - - | <-- nReset
LC5 -> * * * * - - - - - - - - - - - - | * * | <-- |WAITTEST:w0|wState2
LC2 -> * * * * - - - - - - - - - - - - | * * | <-- |WAITTEST:w0|wState1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\work\2440\sw\2440_buffer\buf2440.rpt
buf2440
** EQUATIONS **
clock : INPUT;
dmaMode0 : INPUT;
dmaMode1 : INPUT;
nDACK : INPUT;
nDmaStart : INPUT;
nFRE : INPUT;
nFWE : INPUT;
nGCS0 : INPUT;
nGCS1 : INPUT;
nGCS2 : INPUT;
nGCS3 : INPUT;
nGCS4 : INPUT;
nGCS5 : INPUT;
nGCS6 : INPUT;
nOE : INPUT;
nReset : INPUT;
-- Node name is 'BUFDIR'
-- Equation name is 'BUFDIR', location is LC003, type is output.
BUFDIR = LCELL( _EQ001 $ VCC);
_EQ001 = nFRE & nOE;
-- Node name is 'BUFDIR1'
-- Equation name is 'BUFDIR1', location is LC011, type is output.
BUFDIR1 = LCELL( _EQ002 $ VCC);
_EQ002 = nFRE & nOE;
-- Node name is 'data0'
-- Equation name is 'data0', location is LC019, type is output.
data0 = TRI(_LC019, _LC001);
_LC019 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC002 & _LC005;
-- Node name is 'data1'
-- Equation name is 'data1', location is LC018, type is output.
data1 = TRI(_LC018, _LC001);
_LC018 = LCELL( _EQ004 $ GND);
_EQ004 = !_LC002 & _LC005;
-- Node name is 'data2'
-- Equation name is 'data2', location is LC023, type is output.
data2 = TRI(_LC023, _LC001);
_LC023 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC002 & _LC005;
-- Node name is 'data3~1'
-- Equation name is 'data3~1', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ006 $ GND);
_EQ006 = !nGCS4 & !nOE;
-- Node name is 'data3'
-- Equation name is 'data3', location is LC026, type is output.
data3 = TRI(_LC026, _LC001);
_LC026 = LCELL( _EQ007 $ GND);
_EQ007 = !_LC002 & _LC005;
-- Node name is 'nDREQ'
-- Equation name is 'nDREQ', location is LC032, type is output.
nDREQ = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC024 & _LC025 & !_LC027 & !_LC029;
-- Node name is 'nEXTBUS'
-- Equation name is 'nEXTBUS', location is LC014, type is output.
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