2410audio.c

2440的开发板

/*
 * Philips UDA1380 Audio Device Driver for S3C2410 Linux
 *
 * Copyright (C) 2002 MIZI Research, Inc.
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/sound.h>
#include <linux/soundcard.h>

#include <linux/pm.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/semaphore.h>
#include <asm/dma.h>
#include <asm/arch/cpu_s3c2440.h>

#include "khead.h"
#include "2410audio.h"
#define UDA1380
#define PDEBUG
#undef DEBUG
//#define DEBUG
#ifdef DEBUG
#define DPRINTK( x... )  printk( ##x )
#else
#define DPRINTK( x... )
#endif


/* UDA1380 Register bits */
#define UDA1380_ADDR		0x14

#define UDA1380_REG_DATA	0x0
#define UDA1380_REG_STATUS	0x2

#define SC_512fs		(0x0 << 4)
#define SC_384fs		(0x1 << 4)
#define SC_256fs		(0x2 << 4)

#define IF_IIS			(0x0 << 1)
#define IF_LSB_16		(0x1 << 1)
#define IF_LSB_18		(0x2 << 1)
#define IF_LSB_20		(0x3 << 1)
#define IF_MSB			(0x4 << 1)

#define MUTE		        (0x1 << 2)

#define NO_DE_EMPHASIS		(0x10 << 3)
#define DE_EMPHASIS_32		(0x11 << 3)
#define DE_EMPHASIS_441		(0x12 << 3)
#define DE_EMPHASIS_48		(0x13 << 3)

#define GPIO_L3CLOCK            (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_B4)
#define GPIO_L3DATA             (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_B3)
#define GPIO_L3MODE             (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_B2)

#define AUDIO_NAME		"UDA1380"
#define AUDIO_NAME_VERBOSE	"UDA1380 audio driver"

#define AUDIO_FMT_MASK          (AFMT_S16_LE)
#define AUDIO_FMT_DEFAULT       (AFMT_S16_LE)

#define AUDIO_CHANNELS_DEFAULT	2
#define AUDIO_RATE_DEFAULT	22050 //8000

#define AUDIO_NBFRAGS_DEFAULT	8 //16
#define AUDIO_FRAGSIZE_DEFAULT	8192

#define S_CLOCK_FREQ	384
#define PCM_ABS(a) (a < 0 ? -a : a)

#define IICBUFSIZE 0x20
#define BIT_IIC        (0x1<<27)

#define rGPECON    (*(volatile U32 *)r_GPECON) //Port E control
#define rGPEUP     (*(volatile U32 *)r_GPEUP) //Pull-up control E
#define rIICCON  (*(volatile unsigned char *)r_IICCON) //IIC control
#define rIICSTAT (*(volatile unsigned char *)r_IICSTAT) //IIC status
#define rIICADD  (*(volatile unsigned char *)r_IICADD) //IIC address
#define rIICDS   (*(volatile unsigned char *)r_IICDS) //IIC data shift

#define WRDATA      (1)
#define POLLACK     (2)
#define RDDATA      (3)
#define SETRDADDR   (4)

#define Uart_Printf PDEBUG
extern int uda1380_init(void);
#define U8 unsigned char
#define U32 unsigned int
static unsigned char _iicData[IICBUFSIZE];
static volatile int _iicDataCount;
static volatile int _iicStatus;
static volatile int _iicMode;
static int _iicPt;

typedef struct {
	int size;		/* buffer size */
	char *start;		/* point to actual buffer */
	dma_addr_t dma_addr;	/* physical buffer address */
	struct semaphore sem;	/* down before touching the buffer */
	int master;		/* owner for buffer allocation, contain size when true */
} audio_buf_t;

typedef struct {
	audio_buf_t *buffers;	/* pointer to audio buffer structures */
	audio_buf_t *buf;	/* current buffer used by read/write */
	u_int buf_idx;		/* index for the pointer above */
	u_int fragsize;		/* fragment i.e. buffer size */
	u_int nbfrags;		/* nbr of fragments */
	dmach_t dma_ch;		/* DMA channel (channel2 for audio) */
} audio_stream_t;

static audio_stream_t output_stream;
static audio_stream_t input_stream;
 
#define NEXT_BUF(_s_,_b_) { \
        (_s_)->_b_##_idx++; \
        (_s_)->_b_##_idx %= (_s_)->nbfrags; \
        (_s_)->_b_ = (_s_)->buffers + (_s_)->_b_##_idx; }

extern int uda1380_init(void);
static u_int audio_rate;
static int audio_channels;
static int audio_fmt;
static u_int audio_fragsize;
static u_int audio_nbfrags;


static int audio_rd_refcount;
static int audio_wr_refcount;
#define audio_active		(audio_rd_refcount | audio_wr_refcount)

static int audio_dev_dsp;
static int audio_dev_mixer;
static int audio_mix_modcnt;

static int uda1380_volume;
static u8 uda_sampling;

U32 r_GPECON,r_GPEUP;
U32 r_IICCON,r_IICSTAT,r_IICADD,r_IICDS;
//       SMDK2410 IIC configuration
//  GPE15=IICSDA, GPE14=IICSCL
//  "Interrupt mode" for IIC block
//=================================================================== 
int address_map(void)
{
	r_GPECON	=__ioremap(0x56000040,4,0);
	r_GPEUP		=__ioremap(0x56000048,4,0);
	r_IICCON	=__ioremap(0x54000000,4,0);
	r_IICSTAT	=__ioremap(0x54000004,4,0);
	r_IICADD	=__ioremap(0x54000008,4,0);
	r_IICDS		=__ioremap(0x5400000c,4,0);

	return 0;
}

void Delay(int times)
{
	udelay(1000);
}
int Test_Iic2(void)
{
    unsigned int i,j,save_E,save_PE;
        unsigned int upll, uclk, camclk,camclk_div;
    static U32 data;
    static U32 rdata;
    static U32 wdata;
	address_map();

    save_E   = rGPECON;
    save_PE  = rGPEUP;

    rGPEUP  |= 0xc000;                  //Pull-up disable
    rGPECON |= 0xa00000;                //GPE15:IICSDA , GPE14:IICSCL    
      //Enable ACK, Prescaler IICCLK=PCLK/16, Enable interrupt, Transmit clock value Tx clock=IICCLK/16
    rIICCON  = (1<<7) | (0<<6) | (1<<5) | (0xf);

    rIICADD  = 0x10;                    //2410 slave address = [7:1]
    rIICSTAT = 0x10;                    //IIC bus data output enable(Rx/Tx)

#if 1
        wdata = 0xaa55;
      	i=0x11;	
        _Wr24C080(0x30,(U8)i,wdata);
	printk("the date write is: %x\n",wdata);

       _Rd24C080(0x31,(U8)i,&(rdata)); 
    	printk("the read data is: %x \n",rdata);
#endif
    rGPEUP  = save_PE;
    rGPECON = save_E;
	return 0;
}

//**************[ _Wr24C080 ]*****************************************
void _Wr24C080(U32 slvAddr,U32 addr,U32 wdata)
{
    _iicMode      = WRDATA;
    _iicPt        = 0;
    _iicData[0]   = (U8)addr;
    _iicData[1]   = wdata/256;
    _iicData[2]   = wdata;
    _iicDataCount = 3;
    Uart_Printf("MSB is: %2x \n",_iicData[1]);
    Uart_Printf("LSB is: %2x \n",_iicData[2]);
    rIICDS        = slvAddr&0xfe;            //0x30
      //Master Tx mode, Start(Write), IIC-bus data output enable
      //Bus arbitration sucessful, Address as slave status flag Cleared,
      //Address zero status flag cleared, Last received bit is 0
    rIICSTAT      = 0xf0;      
      //Clearing the pending bit isn't needed because the pending bit has been cleared.
    while(_iicDataCount!=-1)
       Run_IicPoll();

    _iicMode = POLLACK;
    while(1)
    {
        rIICDS     =slvAddr&0xfe;
        _iicStatus = 0x100;             //To check if _iicStatus is changed 
        rIICSTAT   = 0xf0;              //Master Tx, Start, Output Enable, Sucessful, Cleared, Cleared, 0
        rIICCON    = 0xaf;              //Resumes IIC operation. 
	while(_iicStatus==0x100)  
            Run_IicPoll();
              
        if(!(_iicStatus & 0x1))
	PDEBUG("ACK is received\n");
            break;                      //When ACK is received
    }
    rIICSTAT = 0xd0;                    //Master Tx condition, Stop(Write), Output Enable
    rIICCON  = 0xaf;                    //Resumes IIC operation. 
    Delay(1);                           //Wait until stop condtion is in effect.
      //Write is completed.
}
        
//************************[ _Rd24C080 ]********************************
void _Rd24C080(U32 slvAddr,U32 addr,U32 *rdata)
{
	PDEBUG("read---->0\n");
    _iicMode      = SETRDADDR;
    _iicPt        = 0;
    _iicData[0]   = (U8)addr;
    _iicDataCount = 1;
	PDEBUG("read---->1\n");
    
    rIICDS   = slvAddr&0xfe;			//0x31
    rIICSTAT = 0xf0;                    //MasTx,Start  
      //Clearing the pending bit isn't needed because the pending bit has been cleared.
	PDEBUG("read---->2\n");
    while(_iicDataCount!=-1)
        Run_IicPoll();
	
    _iicMode      = RDDATA;
    _iicPt        = 0;
    _iicDataCount = 2;
    
    rIICDS   = slvAddr|0x01;
    rIICSTAT = 0xb0;                    //Master Rx,Start
    rIICCON  = 0xaf;                    //Resumes IIC operation.  
     while(_iicDataCount!=-1)
        Run_IicPoll();

    *rdata = _iicData[1]*256+_iicData[2];
//    Uart_Printf("the read date is: %2x \n",_iicData[1]);
//    Uart_Printf("the read date is: %2x \n",_iicData[2]);
	
}
//**********************[ Run_IicPoll ]*********************************
void Run_IicPoll(void)
{
    if(rIICCON & 0x10)                  //Tx/Rx Interrupt Enable
       IicPoll();
}       
    
//**********************[IicPoll ]**************************************
void IicPoll(void)
{
    U32 iicSt,i;
    iicSt = rIICSTAT; 
    if(iicSt & 0x8){
	PDEBUG("bus arbitration is failed\n");
			}   //When bus arbitration is failed.
    if(iicSt & 0x4){
	PDEBUG("matched\n");
	}                   //When a slave address is matched with IICADD
    if(iicSt & 0x2){
	PDEBUG("slave address 0000000b\n");
	}                   //When a slave address is 0000000b
    if(iicSt & 0x1){
	PDEBUG("Ack isn't received\n");
	}                   //When ACK isn't received

    switch(_iicMode)
    {
        case POLLACK:
		PDEBUG("poll--ACK\n");
            _iicStatus = iicSt;
            break;

        case RDDATA:
	//	PDEBUG("read--ACK\n");
            if((_iicDataCount--)==0)
            {
                _iicData[_iicPt++] = rIICDS;
            
                rIICSTAT = 0x90;                //Stop MasRx condition 
                rIICCON  = 0xaf;                //Resumes IIC operation.
                Delay(1);                       //Wait until stop condtion is in effect.
                                                //Too long time... 
                                                //The pending bit will not be set after issuing stop condition.
                break;    
            }      
            _iicData[_iicPt++] = rIICDS;
                        //The last data has to be read with no ack.
            if((_iicDataCount)==0)
                rIICCON = 0x2f;                 //Resumes IIC operation with NOACK.  
            else 
                rIICCON = 0xaf;                 //Resumes IIC operation with ACK
            break;

        case WRDATA:
	//	PDEBUG("write--ACK\n");
            if((_iicDataCount--)==0)
            {
                rIICSTAT = 0xd0;                //stop MasTx condition 
                rIICCON  = 0xaf;                //resumes IIC operation.
                Delay(1);                       //wait until stop condtion is in effect.
                       //The pending bit will not be set after issuing stop condition.
                break;    
            }
		PDEBUG("poll--->write\n");
            rIICDS = _iicData[_iicPt++];        //_iicData[0] has dummy.
            for(i=0;i<10;i++);                  //for setup time until rising edge of IICSCL
            rIICCON = 0xaf;                     //resumes IIC operation.
            break;

        case SETRDADDR:
//            Uart_Printf("IicPoll() SETRADDR [S%d]\n",_iicDataCount);
	//	PDEBUG("SETRDADDR\n");
            if((_iicDataCount--)==0)
            {
                break;                  //IIC operation is stopped because of IICCON[4]    
            }
            rIICDS = _iicData[_iicPt++];
            for(i=0;i<10;i++);          //for setup time until rising edge of IICSCL
            rIICCON = 0xaf;             //resumes IIC operation.
            break;

        default:
            break;      
    }
}

unsigned char command[] = {
	0x00, 0x0F, 0x02, //Sysclock
	//0x00, 0x0F, 0x32,	//WSPLL 44.1KHz
	0x01, 0x00, 0x00,
	0x02, 0xaf, 0xff,	//line in
	0x03, 0x00, 0x00,
	0x04, 0x02, 0x02,   //default
	0x10, 0x00, 0x00,
	0x11, 0x00, 0x00,
	0x12, 0x00, 0x00,
	0x13, 0x00, 0x00,
	0x14, 0x00, 0x00,
	0x20, 0x00, 0x00,
	0x21, 0x00, 0x00,
	//0x22, 0x00, 0x00, 	//line-in
	0x22, 0x00, 0x0C,		//mic
	0x23, 0x00, 0x00
};
int uda1380_init(void)
{
    unsigned int i,j,save_E,save_PE;
    static U32 data;
    static U32 rdata;
    static U32 wdata;
	address_map();
    save_E   = rGPECON;
    save_PE  = rGPEUP;
    rGPEUP  |= 0xc000;                  //Pull-up disable
    rGPECON |= 0xa0000000;                //GPE15:IICSDA , GPE14:IICSCL    
      //Enable ACK, Prescaler IICCLK=PCLK/16, Enable interrupt, Transmit clock value Tx clock=IICCLK/16
    rIICCON  = (1<<7) | (0<<6) | (1<<5) | (0xf);

    rIICADD  = 0x10;                    //2410 slave address = [7:1]
    rIICSTAT = 0x10;     
    Test_Iic2();               //IIC bus data output enable(Rx/Tx)
#if 0
        wdata = 0xba65;
      	i=0x10;	
        _Wr24C080(0x30,(U8)i,wdata);
	printk("the date write is: %x\n",wdata);
       _Rd24C080(0x31,(U8)i,&(rdata)); 
    	printk("the read data is: %x \n",rdata);