taihu405ep_cpld.vhd

amcc PPC405EP taihu 开发板 CPLD 源码

--*****************************************************************************--
--              CPLD for the Taihu405EP Evaluation Board Ver10                 --
--*****************************************************************************--
--*************** CPU R/W PORT, CPU STRAPPING, CONTROL SIGNALS ****************--
--*****************************************************************************--
--**************************** Quartus II 5.0 *********************************--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Taihu405EP_CPLD IS
PORT
	(
--	RESET SIGNALS
	RESET				: IN STD_LOGIC;		-- RESET BUTTON INPUT
	PHY_RESET			: OUT STD_LOGIC;	-- ETHERNET PHY RESET
	SYS_RESET			: INOUT STD_LOGIC;	-- CPU RESET
	PCI_CARDBUS_RESET		: OUT STD_LOGIC;	-- CARDBUS CONTROLLER RESET
--	CHIP SELECT, R/W, CLOCK, ADDRESS BUS, DATA BUS 
	EBC_CS2				: IN STD_LOGIC;
	EBC_CS3				: IN STD_LOGIC;
	EBC_CS4				: IN STD_LOGIC;
	EBC_WE				: IN STD_LOGIC;
	EBC_OE				: IN STD_LOGIC;	
--	////////
	EBC_CLK				: IN STD_LOGIC;		-- 55.5MHz
--	////////
	EBC_A				: IN STD_LOGIC_VECTOR(4 to 7);		
	EBC_D				: INOUT STD_LOGIC_VECTOR(0 to 7);
--	16245 BIDIRECTIONAL TRANSCEIVER OUTPUT ENABLE, LCM ENABLE
	T245_OE				: OUT STD_LOGIC;	
	LCM_E				: OUT STD_LOGIC;	
--	USER SWITCH, USB SUSPEND DETECT, USB RESET, LCM BACKLIGHT CONTROL 
	SWITCH_STS			: IN STD_LOGIC_VECTOR(0 to 3);
	USB_SUSPEND			: IN STD_LOGIC;
	USB_RESET			: OUT STD_LOGIC;
	LCM_CTRL			: OUT STD_LOGIC;
--  CPU STRAPPING	
	CPLD_UART1_TX   		: IN STD_LOGIC;
	CPLD_UART1_RTS      		: IN STD_LOGIC;	
	CPLD_SYS_ERROR      		: IN STD_LOGIC;	
	PCI_M66EN_hardwire  		: IN STD_LOGIC;
	UART1_TX			: OUT STD_LOGIC;	-- TRI-STATE OUTPUT
	UART1_RTS			: OUT STD_LOGIC;	-- TRI-STATE OUTPUT			
	SYS_ERROR			: INOUT STD_LOGIC;
	SYS_ERROR_L			: OUT STD_LOGIC;
--	PCI SLOT 66MHz DETECT	
	PRSNT1				: IN STD_LOGIC;
	PRSNT2				: IN STD_LOGIC;	
	M66EN				: IN STD_LOGIC;	
	PCI_M66EN			: OUT STD_LOGIC;	
	PCI_M33EN			: OUT STD_LOGIC;	
--  JTAG PORT RESET	
	JTAG_TRST			: IN STD_LOGIC;
	CPLD_TRST			: OUT STD_LOGIC
	);
END Taihu405EP_CPLD;


ARCHITECTURE RTL OF Taihu405EP_CPLD IS

SIGNAL PCI_M66EN_TMP : STD_LOGIC;

SIGNAL EBC_CS2_TMP : STD_LOGIC;

SIGNAL BOARD_RESET : STD_LOGIC;

SIGNAL VER : STD_LOGIC_VECTOR(0 TO 1);

SIGNAL REG0,REG1 : STD_LOGIC_VECTOR(0 TO 7);


BEGIN

VER <= "10";

--	RESET
PROCESS (RESET)
BEGIN
	
	IF RESET = '0' THEN
		SYS_RESET <= RESET;
	ELSE
		SYS_RESET <= 'Z';
	END IF;
	
END PROCESS;
BOARD_RESET <= RESET AND SYS_RESET;
PHY_RESET <= BOARD_RESET;
PCI_CARDBUS_RESET <= BOARD_RESET;

--	T245_OE
PROCESS (EBC_CLK)
BEGIN

	IF EBC_CLK'EVENT AND EBC_CLK = '1' THEN
			EBC_CS2_TMP <= EBC_CS2;
	END IF;
	
END PROCESS;
T245_OE <= EBC_CS2 AND EBC_CS2_TMP AND EBC_CS3 AND EBC_CS4;

--  LCM_E, EBC_A(6) = 1, LCM ENABLE
LCM_E <= NOT ((EBC_CS3 OR EBC_WE) AND (EBC_CS3 OR EBC_OE)) AND EBC_A(6);

--	SYS_ERROR_L, SYSTEM ERROR LED INDICATOR
SYS_ERROR_L <= NOT SYS_ERROR;

--  PCI 66MHz ENABLE
PCI_M66EN_TMP <= NOT (PRSNT1 AND PRSNT2) AND M66EN AND PCI_M66EN_hardwire;

PCI_M66EN <= PCI_M66EN_TMP;
PCI_M33EN <= NOT PCI_M66EN_TMP;

--	JTAG PORT RESET
CPLD_TRST <= JTAG_TRST AND BOARD_RESET;

--	CPU WRITES CPLD REGISTER1: REG1(0 TO 7)
PROCESS (BOARD_RESET,EBC_CLK)
BEGIN

	IF BOARD_RESET = '0' THEN
		REG1(6 TO 7) <= "01";		--  LCM_CTRL & USB_RESET
	ELSIF EBC_CLK'EVENT AND EBC_CLK = '1' THEN
		IF EBC_CS3 = '0' AND EBC_WE = '0' AND EBC_A(6 TO 7) = "01" THEN
			REG1(6) <= EBC_D(6);
			REG1(7) <= EBC_D(7); 
		END IF;
	END IF;
	
END PROCESS;

REG1(0 TO 5) <= "000000";			-- RESERVED
LCM_CTRL <= REG1(6);				-- LCM_CTRL
USB_RESET <= REG1(7) AND BOARD_RESET;		-- USB_RESET

--	CPU READS CPLD REGISTER0,REGISTER1: REG0(0 TO 7), REG1(0 TO 7)
REG0 <= VER & USB_SUSPEND & PCI_M66EN_TMP & SWITCH_STS;


PROCESS (EBC_CS3,EBC_OE,EBC_A(6 TO 7),REG0,REG1)
BEGIN

	IF EBC_CS3 = '0' AND EBC_OE = '0' AND EBC_A(6) = '0' THEN
		IF EBC_A(7) = '0' THEN
			EBC_D <= REG0;
		ELSE
			EBC_D <= REG1;
		END IF;
	ELSE
		EBC_D <= (OTHERS => 'Z');
	END IF;
	
END PROCESS;

--  CPU STRAPPING
PROCESS (BOARD_RESET,CPLD_UART1_TX,CPLD_UART1_RTS,CPLD_SYS_ERROR)
BEGIN
	
	IF BOARD_RESET = '0' THEN
		UART1_TX <= CPLD_UART1_TX;
		UART1_RTS <= CPLD_UART1_RTS;
		SYS_ERROR <= CPLD_SYS_ERROR;
	ELSE
		UART1_TX <= 'Z';
		UART1_RTS <= 'Z';
		SYS_ERROR <= 'Z';
	END IF;
	
END PROCESS;

END RTL;