lcd.ptf

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

               }
               CONSTANT PLUGS_PING
               {
                  value = "1";
                  comment = "Respond to icmp echo (ping) messages";
               }
               CONSTANT PLUGS_TCP
               {
                  value = "1";
                  comment = "Support tcp in/out connections";
               }
               CONSTANT PLUGS_IRQ
               {
                  value = "1";
                  comment = "Run at interrupte level";
               }
               CONSTANT PLUGS_DEBUG
               {
                  value = "1";
                  comment = "Support debug routines";
               }
            }
         }
         SYSTEM_BUILDER_INFO
         {
            Is_Enabled = "1";
         }
      }
      SIMULATION
      {
         DISPLAY
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Divider";
               name = "common";
               radix = "";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "R_vinst";
               radix = "ascii";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "F_valid";
               radix = "hexadecimal";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "R_valid";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "D_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "D_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL abg
            {
               format = "Divider";
               name = "breaks";
               radix = "";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "hbreak_req";
               radix = "hexadecimal";
            }
            SIGNAL abi
            {
               format = "Logic";
               name = "oci_hbreak_req";
               radix = "hexadecimal";
            }
            SIGNAL abj
            {
               format = "Logic";
               name = "hbreak_enabled";
               radix = "hexadecimal";
            }
            SIGNAL abk
            {
               format = "Logic";
               name = "wait_for_one_post_bret_inst";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE onchip_mem
   {
      SLAVE s1
      {
         PORT_WIRING
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT clken
            {
               type = "clken";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "1";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x00001400";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00001400";
            }
            Base_Address = "0x00001400";
            Address_Group = "0";
            Has_IRQ = "0";
            Is_Channel = "1";
            Is_Writable = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      iss_model_name = "altera_memory";
      WIZARD_SCRIPT_ARGUMENTS
      {
         allow_mram_sim_contents_only_file = "0";
         ram_block_type = "M4K";
         init_contents_file = "onchip_mem";
         non_default_init_file_enabled = "0";
         gui_ram_block_type = "Automatic";
         Writeable = "1";
         dual_port = "0";
         Size_Value = "1024";
         Size_Multiple = "1";
         use_shallow_mem_blocks = "0";
         init_mem_content = "1";
         allow_in_system_memory_content_editor = "0";
         instance_id = "NONE";
         ignore_auto_block_type_assignment = "1";
      }
      SIMULATION
      {
         DISPLAY
         {
            SIGNAL a
            {
               name = "chipselect";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "byteenable";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "write";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "writedata";
               radix = "hexadecimal";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO
      {
         Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "onchip_memory";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         Has_Clock = "1";
         View
         {
            MESSAGES
            {
            }
         }
      }
      class = "altera_avalon_onchip_memory2";
      class_version = "7.071";
      HDL_INFO
      {
      }
      SLAVE s2
      {
         PORT_WIRING
         {
         }
         SYSTEM_BUILDER_INFO
         {
            Bus_Type = "avalon";
            Is_Memory_Device = "1";
            Address_Group = "0";
            Address_Alignment = "dynamic";
            Address_Width = "8";
            Data_Width = "32";
            Has_IRQ = "0";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            Address_Span = "1024";
            Read_Latency = "1";
            Is_Channel = "1";
            Is_Enabled = "0";
            Is_Writable = "1";
         }
      }
   }
}