📄 cpu_test_bench.vhd
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write(write_line12, string'("ERROR: cpu_test_bench/i_read is 'x'"));
write(output, write_line12.all & CR);
deallocate (write_line12);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line13 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(i_read) = '1' then
if is_x(i_address) then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("ERROR: cpu_test_bench/i_address is 'x'"));
write(output, write_line13.all & CR);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line14 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((i_read AND NOT i_waitrequest)) = '1' then
if is_x(i_readdata) then
write(write_line14, now);
write(write_line14, string'(": "));
write(write_line14, string'("ERROR: cpu_test_bench/i_readdata is 'x'"));
write(output, write_line14.all & CR);
deallocate (write_line14);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line15 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_ctrl_ld)) = '1' then
if is_x(av_ld_data_aligned_unfiltered) then
write(write_line15, now);
write(write_line15, string'(": "));
write(write_line15, string'("WARNING: cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'"));
write(output, write_line15.all & CR);
deallocate (write_line15);
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line16 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(W_wr_data) then
write(write_line16, now);
write(write_line16, string'(": "));
write(write_line16, string'("WARNING: cpu_test_bench/W_wr_data is 'x'"));
write(output, write_line16.all & CR);
deallocate (write_line16);
end if;
end if;
end if;
end process;
process is
variable status : file_open_status; -- status for fopen
VARIABLE write_line17 : line;
VARIABLE write_line18 : line;
begin -- process
file_open(status, trace_handle, "cpu.tr", WRITE_MODE);
write(write_line17, string'("version 2"));
write(trace_handle, write_line17.all & LF);
deallocate (write_line17);
write(write_line18, string'("numThreads 1"));
write(trace_handle, write_line18.all & LF);
deallocate (write_line18);
wait; -- wait forever
end process;
process (clk)
VARIABLE write_line19 : line;
begin
if clk'event and clk = '1' then
if std_logic'((NOT reset_n OR (W_valid))) = '1' then
write(write_line19, now);
write(write_line19, string'(": "));
write(write_line19, to_hex_string(NOT reset_n, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(F_pcb, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(D_op_intr, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(D_op_hbreak, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(D_iw, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(rf_wr, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(R_dst_regnum, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(rf_wr_data, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_mem_baddr, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(E_st_data, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(E_mem_byte_en, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_cmp_result, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(E_alu_result, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_status_reg, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_estatus_reg, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_bstatus_reg, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_ienable_reg, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(W_ipending_reg, pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line19, string'(","));
write(write_line19, to_hex_string(R_ctrl_exception, pad_none));
write(write_line19, string'(""));
write(trace_handle, write_line19.all & LF);
deallocate (write_line19);
end if;
end if;
end process;
D_inst <= A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000010"))), std_logic_vector'("00100000001000000111001001110011011101100011000000110010"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000010000"))), std_logic_vector'("00100000011000110110110101110000011011000111010001101001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000010010"))), std_logic_vector'("00100000001000000111001001110011011101100011000100111000"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000011010"))), std_logic_vector'("00100000001000000111001001110011011101100011001000110110"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000101010"))), std_logic_vector'("00100000001000000111001001110011011101100011010000110010"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000100111"))), std_logic_vector'("00100000001000000110110001100100011000100110100101101111"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000011"))), std_logic_vector'("00100000001000000010000001101100011001000110001001110101"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000110100"))), std_logic_vector'("00100000001000000010000001101111011100100110100001101001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000011111"))), std_logic_vector'("00100000001000000111001001110011011101100011001100110001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000001110"))), std_logic_vector'("00100000001000000010000000100000011000100110011101100101"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000110"))), std_logic_vector'("00100000001000000010000000100000001000000110001001110010"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000101111"))), std_logic_vector'("00100000001000000110110001100100011010000110100101101111"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000101001"))), std_logic_vector'("00100000001000000111001001110011011101100011010000110001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000010011"))), std_logic_vector'("00100000001000000111001001110011011101100011000100111001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000110111"))), std_logic_vector'("00100000001000000110110001100100011101110110100101101111"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000011101"))), std_logic_vector'("00100000001000000111001001110011011101100011001000111001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000111101"))), std_logic_vector'("00100000001000000111001001110011011101100011011000110001"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000101"))), std_logic_vector'("00100000001000000010000000100000011100110111010001100010"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000111110"))), std_logic_vector'("00100000001000000111001001110011011101100011011000110010"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000110110"))), std_logic_vector'("00100000001000000010000001100010011011000111010001110101"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000110010"))), std_logic_vector'("00100000011000110111010101110011011101000110111101101101"), A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000") & (D_iw_op(5 DOWNTO 0))) = std_logic_vector'("00000000000⌨️ 快捷键说明
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