ex.tan.rpt

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

; N/A   ; None         ; 10.696 ns  ; cnt[10] ; seg[3]  ; clk        ;
; N/A   ; None         ; 10.518 ns  ; cnt[24] ; led8[0] ; clk        ;
; N/A   ; None         ; 10.338 ns  ; cnt[26] ; led8[0] ; clk        ;
; N/A   ; None         ; 10.178 ns  ; cnt[25] ; led8[0] ; clk        ;
; N/A   ; None         ; 9.942 ns   ; cnt[12] ; sel[1]  ; clk        ;
; N/A   ; None         ; 9.941 ns   ; cnt[12] ; sel[0]  ; clk        ;
; N/A   ; None         ; 9.865 ns   ; cnt[11] ; sel[1]  ; clk        ;
; N/A   ; None         ; 9.864 ns   ; cnt[11] ; sel[0]  ; clk        ;
; N/A   ; None         ; 9.799 ns   ; cnt[27] ; led8[0] ; clk        ;
; N/A   ; None         ; 9.753 ns   ; cnt[1]  ; DDS[1]  ; clk        ;
; N/A   ; None         ; 9.653 ns   ; cnt[10] ; sel[0]  ; clk        ;
; N/A   ; None         ; 9.646 ns   ; cnt[10] ; sel[1]  ; clk        ;
; N/A   ; None         ; 9.631 ns   ; cnt[4]  ; DA1[4]  ; clk        ;
; N/A   ; None         ; 9.550 ns   ; cnt[2]  ; DA1[2]  ; clk        ;
; N/A   ; None         ; 9.550 ns   ; cnt[2]  ; DDS[2]  ; clk        ;
; N/A   ; None         ; 9.360 ns   ; cnt[0]  ; DDS[0]  ; clk        ;
; N/A   ; None         ; 9.340 ns   ; cnt[3]  ; DA1[3]  ; clk        ;
; N/A   ; None         ; 9.336 ns   ; cnt[5]  ; DA1[5]  ; clk        ;
; N/A   ; None         ; 9.336 ns   ; cnt[5]  ; DDS[5]  ; clk        ;
; N/A   ; None         ; 9.299 ns   ; cnt[0]  ; DA1[0]  ; clk        ;
; N/A   ; None         ; 8.895 ns   ; cnt[4]  ; DDS[4]  ; clk        ;
; N/A   ; None         ; 8.887 ns   ; cnt[1]  ; DA1[1]  ; clk        ;
; N/A   ; None         ; 8.885 ns   ; cnt[6]  ; DA1[6]  ; clk        ;
; N/A   ; None         ; 8.849 ns   ; cnt[7]  ; DA1[7]  ; clk        ;
; N/A   ; None         ; 8.740 ns   ; cnt[3]  ; DDS[3]  ; clk        ;
+-------+--------------+------------+---------+---------+------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+---------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To   ;
+-------+-------------------+-----------------+---------+------+
; N/A   ; None              ; 7.493 ns        ; key2[2] ; d7   ;
; N/A   ; None              ; 7.365 ns        ; key2[1] ; d6   ;
; N/A   ; None              ; 7.326 ns        ; key2[0] ; d5   ;
; N/A   ; None              ; 7.284 ns        ; key2[3] ; d8   ;
; N/A   ; None              ; 7.238 ns        ; key1[1] ; beep ;
; N/A   ; None              ; 6.107 ns        ; key1[2] ; d4   ;
; N/A   ; None              ; 6.107 ns        ; key1[2] ; d3   ;
; N/A   ; None              ; 5.890 ns        ; key1[3] ; d2   ;
; N/A   ; None              ; 5.890 ns        ; key1[3] ; d1   ;
+-------+-------------------+-----------------+---------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Aug 26 11:36:44 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ex -c ex
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 168.24 MHz between source register "cnt[1]" and destination register "cnt[23]" (period= 5.944 ns)
    Info: + Longest register to register delay is 5.235 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y5_N2; Fanout = 5; REG Node = 'cnt[1]'
        Info: 2: + IC(1.303 ns) + CELL(0.978 ns) = 2.281 ns; Loc. = LC_X6_Y5_N2; Fanout = 2; COMB Node = 'cnt[1]~197'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.404 ns; Loc. = LC_X6_Y5_N3; Fanout = 2; COMB Node = 'cnt[2]~199'
        Info: 4: + IC(0.000 ns) + CELL(0.261 ns) = 2.665 ns; Loc. = LC_X6_Y5_N4; Fanout = 6; COMB Node = 'cnt[3]~201'
        Info: 5: + IC(0.000 ns) + CELL(0.349 ns) = 3.014 ns; Loc. = LC_X6_Y5_N9; Fanout = 6; COMB Node = 'cnt[8]~231'
        Info: 6: + IC(0.000 ns) + CELL(0.246 ns) = 3.260 ns; Loc. = LC_X7_Y5_N4; Fanout = 6; COMB Node = 'cnt[13]~249'
        Info: 7: + IC(0.000 ns) + CELL(0.349 ns) = 3.609 ns; Loc. = LC_X7_Y5_N9; Fanout = 6; COMB Node = 'cnt[18]~239'
        Info: 8: + IC(0.000 ns) + CELL(1.626 ns) = 5.235 ns; Loc. = LC_X8_Y5_N4; Fanout = 2; REG Node = 'cnt[23]'
        Info: Total cell delay = 3.932 ns ( 75.11 % )
        Info: Total interconnect delay = 1.303 ns ( 24.89 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.547 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'
            Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X8_Y5_N4; Fanout = 2; REG Node = 'cnt[23]'
            Info: Total cell delay = 2.081 ns ( 58.67 % )
            Info: Total interconnect delay = 1.466 ns ( 41.33 % )
        Info: - Longest clock path from clock "clk" to source register is 3.547 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'
            Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X6_Y5_N2; Fanout = 5; REG Node = 'cnt[1]'
            Info: Total cell delay = 2.081 ns ( 58.67 % )
            Info: Total interconnect delay = 1.466 ns ( 41.33 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "led8[5]" through register "cnt[26]" is 12.161 ns
    Info: + Longest clock path from clock "clk" to source register is 3.547 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'
        Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X8_Y5_N7; Fanout = 10; REG Node = 'cnt[26]'
        Info: Total cell delay = 2.081 ns ( 58.67 % )
        Info: Total interconnect delay = 1.466 ns ( 41.33 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin d