prev_cmp_led.tan.qmsg

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\] AD\[7\] clk 6.549 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\]\" (data pin = \"AD\[7\]\", clock pin = \"clk\") is 6.549 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.297 ns + Longest pin register " "Info: + Longest pin to register delay is 9.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns AD\[7\] 1 PIN PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; PIN Node = 'AD\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AD[7] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 296 -184 -16 312 "AD\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.707 ns) + CELL(0.115 ns) 9.297 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\] 2 REG LC_X21_Y10_N1 3 " "Info: 2: + IC(7.707 ns) + CELL(0.115 ns) = 9.297 ns; Loc. = LC_X21_Y10_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.822 ns" { AD[7] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 937 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 17.10 % ) " "Info: Total cell delay = 1.590 ns ( 17.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.707 ns ( 82.90 % ) " "Info: Total interconnect delay = 7.707 ns ( 82.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.297 ns" { AD[7] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.297 ns" { AD[7] {} AD[7]~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] {} } { 0.000ns 0.000ns 7.707ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 937 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 399 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 399; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 152 -176 -8 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.711 ns) 2.785 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\] 2 REG LC_X21_Y10_N1 3 " "Info: 2: + IC(0.605 ns) + CELL(0.711 ns) = 2.785 ns; Loc. = LC_X21_Y10_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 937 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.28 % ) " "Info: Total cell delay = 2.180 ns ( 78.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.605 ns ( 21.72 % ) " "Info: Total interconnect delay = 0.605 ns ( 21.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] {} } { 0.000ns 0.000ns 0.605ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.297 ns" { AD[7] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.297 ns" { AD[7] {} AD[7]~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] {} } { 0.000ns 0.000ns 7.707ns } { 0.000ns 1.475ns 0.115ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7] {} } { 0.000ns 0.000ns 0.605ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk DAC\[0\] led:inst1\|cnt\[3\] 11.784 ns register " "Info: tco from clock \"clk\" to destination pin \"DAC\[0\]\" through register \"led:inst1\|cnt\[3\]\" is 11.784 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 399 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 399; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 152 -176 -8 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns led:inst1\|cnt\[3\] 2 REG LC_X25_Y8_N5 19 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X25_Y8_N5; Fanout = 19; REG Node = 'led:inst1\|cnt\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk led:inst1|cnt[3] } "NODE_NAME" } } { "LED.vhd" "" { Text "C:/altera/Hengdun/LED/LED.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk led:inst1|cnt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} led:inst1|cnt[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LED.vhd" "" { Text "C:/altera/Hengdun/LED/LED.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.778 ns + Longest register pin " "Info: + Longest register to pin delay is 8.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:inst1\|cnt\[3\] 1 REG LC_X25_Y8_N5 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y8_N5; Fanout = 19; REG Node = 'led:inst1\|cnt\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:inst1|cnt[3] } "NODE_NAME" } } { "LED.vhd" "" { Text "C:/altera/Hengdun/LED/LED.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.590 ns) 1.925 ns Rom:inst\|Ram0~709 2 COMB LC_X24_Y9_N7 2 " "Info: 2: + IC(1.335 ns) + CELL(0.590 ns) = 1.925 ns; Loc. = LC_X24_Y9_N7; Fanout = 2; COMB Node = 'Rom:inst\|Ram0~709'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.925 ns" { led:inst1|cnt[3] Rom:inst|Ram0~709 } "NODE_NAME" } } { "rom.vhd" "" { Text "C:/altera/Hengdun/LED/rom.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.590 ns) 2.964 ns Rom:inst\|Ram0~711 3 COMB LC_X24_Y9_N1 2 " "Info: 3: + IC(0.449 ns) + CELL(0.590 ns) = 2.964 ns; Loc. = LC_X24_Y9_N1; Fanout = 2; COMB Node = 'Rom:inst\|Ram0~711'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.039 ns" { Rom:inst|Ram0~709 Rom:inst|Ram0~711 } "NODE_NAME" } } { "rom.vhd" "" { Text "C:/altera/Hengdun/LED/rom.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.292 ns) 4.783 ns Rom:inst\|Ram0~713 4 COMB LC_X22_Y10_N3 1 " "Info: 4: + IC(1.527 ns) + CELL(0.292 ns) = 4.783 ns; Loc. = LC_X22_Y10_N3; Fanout = 1; COMB Node = 'Rom:inst\|Ram0~713'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.819 ns" { Rom:inst|Ram0~711 Rom:inst|Ram0~713 } "NODE_NAME" } } { "rom.vhd" "" { Text "C:/altera/Hengdun/LED/rom.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.871 ns) + CELL(2.124 ns) 8.778 ns DAC\[0\] 5 PIN PIN_106 0 " "Info: 5: + IC(1.871 ns) + CELL(2.124 ns) = 8.778 ns; Loc. = PIN_106; Fanout = 0; PIN Node = 'DAC\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.995 ns" { Rom:inst|Ram0~713 DAC[0] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 152 456 632 168 "DAC\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.596 ns ( 40.97 % ) " "Info: Total cell delay = 3.596 ns ( 40.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.182 ns ( 59.03 % ) " "Info: Total interconnect delay = 5.182 ns ( 59.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.778 ns" { led:inst1|cnt[3] Rom:inst|Ram0~709 Rom:inst|Ram0~711 Rom:inst|Ram0~713 DAC[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.778 ns" { led:inst1|cnt[3] {} Rom:inst|Ram0~709 {} Rom:inst|Ram0~711 {} Rom:inst|Ram0~713 {} DAC[0] {} } { 0.000ns 1.335ns 0.449ns 1.527ns 1.871ns } { 0.000ns 0.590ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk led:inst1|cnt[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} led:inst1|cnt[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.778 ns" { led:inst1|cnt[3] Rom:inst|Ram0~709 Rom:inst|Ram0~711 Rom:inst|Ram0~713 DAC[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.778 ns" { led:inst1|cnt[3] {} Rom:inst|Ram0~709 {} Rom:inst|Ram0~711 {} Rom:inst|Ram0~713 {} DAC[0] {} } { 0.000ns 1.335ns 0.449ns 1.527ns 1.871ns } { 0.000ns 0.590ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}