ex.tan.qmsg

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[1\] register cnt\[23\] 168.24 MHz 5.944 ns Internal " "Info: Clock \"clk\" has Internal fmax of 168.24 MHz between source register \"cnt\[1\]\" and destination register \"cnt\[23\]\" (period= 5.944 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.235 ns + Longest register register " "Info: + Longest register to register delay is 5.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LC_X6_Y5_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y5_N2; Fanout = 5; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.978 ns) 2.281 ns cnt\[1\]~197 2 COMB LC_X6_Y5_N2 2 " "Info: 2: + IC(1.303 ns) + CELL(0.978 ns) = 2.281 ns; Loc. = LC_X6_Y5_N2; Fanout = 2; COMB Node = 'cnt\[1\]~197'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.281 ns" { cnt[1] cnt[1]~197 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.404 ns cnt\[2\]~199 3 COMB LC_X6_Y5_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.404 ns; Loc. = LC_X6_Y5_N3; Fanout = 2; COMB Node = 'cnt\[2\]~199'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt[1]~197 cnt[2]~199 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.665 ns cnt\[3\]~201 4 COMB LC_X6_Y5_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.261 ns) = 2.665 ns; Loc. = LC_X6_Y5_N4; Fanout = 6; COMB Node = 'cnt\[3\]~201'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { cnt[2]~199 cnt[3]~201 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.014 ns cnt\[8\]~231 5 COMB LC_X6_Y5_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.349 ns) = 3.014 ns; Loc. = LC_X6_Y5_N9; Fanout = 6; COMB Node = 'cnt\[8\]~231'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.349 ns" { cnt[3]~201 cnt[8]~231 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 3.260 ns cnt\[13\]~249 6 COMB LC_X7_Y5_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.246 ns) = 3.260 ns; Loc. = LC_X7_Y5_N4; Fanout = 6; COMB Node = 'cnt\[13\]~249'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.246 ns" { cnt[8]~231 cnt[13]~249 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.609 ns cnt\[18\]~239 7 COMB LC_X7_Y5_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.349 ns) = 3.609 ns; Loc. = LC_X7_Y5_N9; Fanout = 6; COMB Node = 'cnt\[18\]~239'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.349 ns" { cnt[13]~249 cnt[18]~239 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 5.235 ns cnt\[23\] 8 REG LC_X8_Y5_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(1.626 ns) = 5.235 ns; Loc. = LC_X8_Y5_N4; Fanout = 2; REG Node = 'cnt\[23\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { cnt[18]~239 cnt[23] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.932 ns ( 75.11 % ) " "Info: Total cell delay = 3.932 ns ( 75.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.303 ns ( 24.89 % ) " "Info: Total interconnect delay = 1.303 ns ( 24.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { cnt[1] cnt[1]~197 cnt[2]~199 cnt[3]~201 cnt[8]~231 cnt[13]~249 cnt[18]~239 cnt[23] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { cnt[1] {} cnt[1]~197 {} cnt[2]~199 {} cnt[3]~201 {} cnt[8]~231 {} cnt[13]~249 {} cnt[18]~239 {} cnt[23] {} } { 0.000ns 1.303ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.261ns 0.349ns 0.246ns 0.349ns 1.626ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.547 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 28 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.918 ns) 3.547 ns cnt\[23\] 2 REG LC_X8_Y5_N4 2 " "Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X8_Y5_N4; Fanout = 2; REG Node = 'cnt\[23\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.384 ns" { clk cnt[23] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 58.67 % ) " "Info: Total cell delay = 2.081 ns ( 58.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.466 ns ( 41.33 % ) " "Info: Total interconnect delay = 1.466 ns ( 41.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[23] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[23] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.547 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 28 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.918 ns) 3.547 ns cnt\[1\] 2 REG LC_X6_Y5_N2 5 " "Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X6_Y5_N2; Fanout = 5; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.384 ns" { clk cnt[1] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 58.67 % ) " "Info: Total cell delay = 2.081 ns ( 58.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.466 ns ( 41.33 % ) " "Info: Total interconnect delay = 1.466 ns ( 41.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[1] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[23] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[23] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[1] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { cnt[1] cnt[1]~197 cnt[2]~199 cnt[3]~201 cnt[8]~231 cnt[13]~249 cnt[18]~239 cnt[23] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { cnt[1] {} cnt[1]~197 {} cnt[2]~199 {} cnt[3]~201 {} cnt[8]~231 {} cnt[13]~249 {} cnt[18]~239 {} cnt[23] {} } { 0.000ns 1.303ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.261ns 0.349ns 0.246ns 0.349ns 1.626ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[23] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[23] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[1] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led8\[5\] cnt\[26\] 12.161 ns register " "Info: tco from clock \"clk\" to destination pin \"led8\[5\]\" through register \"cnt\[26\]\" is 12.161 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.547 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 28 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 28; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.918 ns) 3.547 ns cnt\[26\] 2 REG LC_X8_Y5_N7 10 " "Info: 2: + IC(1.466 ns) + CELL(0.918 ns) = 3.547 ns; Loc. = LC_X8_Y5_N7; Fanout = 10; REG Node = 'cnt\[26\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.384 ns" { clk cnt[26] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 58.67 % ) " "Info: Total cell delay = 2.081 ns ( 58.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.466 ns ( 41.33 % ) " "Info: Total interconnect delay = 1.466 ns ( 41.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[26] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[26] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.238 ns + Longest register pin " "Info: + Longest register to pin delay is 8.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[26\] 1 REG LC_X8_Y5_N7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N7; Fanout = 10; REG Node = 'cnt\[26\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[26] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.640 ns) + CELL(0.914 ns) 3.554 ns Mux8~27 2 COMB LC_X4_Y6_N4 1 " "Info: 2: + IC(2.640 ns) + CELL(0.914 ns) = 3.554 ns; Loc. = LC_X4_Y6_N4; Fanout = 1; COMB Node = 'Mux8~27'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { cnt[26] Mux8~27 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.362 ns) + CELL(2.322 ns) 8.238 ns led8\[5\] 3 PIN PIN_6 0 " "Info: 3: + IC(2.362 ns) + CELL(2.322 ns) = 8.238 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'led8\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.684 ns" { Mux8~27 led8[5] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 39.28 % ) " "Info: Total cell delay = 3.236 ns ( 39.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.002 ns ( 60.72 % ) " "Info: Total interconnect delay = 5.002 ns ( 60.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.238 ns" { cnt[26] Mux8~27 led8[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.238 ns" { cnt[26] {} Mux8~27 {} led8[5] {} } { 0.000ns 2.640ns 2.362ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.547 ns" { clk cnt[26] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.547 ns" { clk {} clk~combout {} cnt[26] {} } { 0.000ns 0.000ns 1.466ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.238 ns" { cnt[26] Mux8~27 led8[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.238 ns" { cnt[26] {} Mux8~27 {} led8[5] {} } { 0.000ns 2.640ns 2.362ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key2\[2\] d7 7.493 ns Longest " "Info: Longest tpd from source pin \"key2\[2\]\" to destination pin \"d7\" is 7.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key2\[2\] 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'key2\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { key2[2] } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.039 ns) + CELL(2.322 ns) 7.493 ns d7 2 PIN PIN_49 0 " "Info: 2: + IC(4.039 ns) + CELL(2.322 ns) = 7.493 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'd7'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.361 ns" { key2[2] d7 } "NODE_NAME" } } { "LED.vhd" "" { Text "G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 46.10 % ) " "Info: Total cell delay = 3.454 ns ( 46.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.039 ns ( 53.90 % ) " "Info: Total interconnect delay = 4.039 ns ( 53.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.493 ns" { key2[2] d7 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.493 ns" { key2[2] {} key2[2]~combout {} d7 {} } { 0.000ns 0.000ns 4.039ns } { 0.000ns 1.132ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 26 11:36:48 2008 " "Info: Processing ended: Tue Aug 26 11:36:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}