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📄 altsyncram_ajm3.tdf

📁 cpld系统 EWB Quartus2编译 电子综合设计试验箱程序
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			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a47 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1024,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 1535,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1024,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 1535,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a48 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1024,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 1535,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1024,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 1535,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a49 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1024,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 1535,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1024,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 1535,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a50 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1024,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 1535,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1024,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 1535,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a51 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a52 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a53 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a54 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a55 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a56 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a57 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a58 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 1536,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 17,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 1536,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 17,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
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