📄 altsyncram_2bb1.tdf
字号:
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "onchip_mem.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[9..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].ena0 = clocken0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portawe = ( (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[3..3]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[2..2]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[1..1]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]), (wren_a & byteena_a[0..0]));
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -