decode_iga.tdf

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 4 
SUBDESIGN decode_iga
( 
	data[1..0]	:	input;
	enable	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode584w[2..0]	: WIRE;
	w_anode597w[2..0]	: WIRE;
	w_anode605w[2..0]	: WIRE;
	w_anode613w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode613w[2..2], w_anode605w[2..2], w_anode597w[2..2], w_anode584w[2..2]);
	w_anode584w[] = ( (w_anode584w[1..1] & (! data_wire[1..1])), (w_anode584w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode597w[] = ( (w_anode597w[1..1] & (! data_wire[1..1])), (w_anode597w[0..0] & data_wire[0..0]), enable_wire);
	w_anode605w[] = ( (w_anode605w[1..1] & data_wire[1..1]), (w_anode605w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode613w[] = ( (w_anode613w[1..1] & data_wire[1..1]), (w_anode613w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE