prev_cmp_led.fit.qmsg

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN 17 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN 17" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ADclk " "Info: Destination \"ADclk\" may be non-global or may not use global clock" {  } { { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 456 536 712 472 "ADclk" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[8\] " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[8\]\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 937 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "Block1.bdf" "" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 152 -176 -8 168 "clk" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "LCD:inst3\|LCD_reset_clk_domain_synch_module:LCD_reset_clk_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"LCD:inst3\|LCD_reset_clk_domain_synch_module:LCD_reset_clk_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|W_rf_wren_a " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|W_rf_wren_a\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "C:/altera/Hengdun/LED/cpu.vhd" 4569 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "C:/altera/Hengdun/LED/cpu.vhd" 200 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "C:/altera/Hengdun/LED/cpu.vhd" 199 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "LCD.vhd" "" { Text "C:/altera/Hengdun/LED/LCD.vhd" 2225 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 390 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 389 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 735 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 735 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|ir\[1\]~118 " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|ir\[1\]~118\" may be non-global or may not use global clock" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "C:/altera/Hengdun/LED/cpu_jtag_debug_module.vhd" 147 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "C:/altera/Hengdun/LED/cpu.vhd" 199 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~181 " "Info: Destination \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~181\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "C:/altera/Hengdun/LED/cpu.vhd" 199 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../../72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../../72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset Global clock " "Info: Automatically promoted signal \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" to use Global clock" {  } { { "../../72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 389 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}