prev_cmp_led.qmsg

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_wrapper LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper " "Info: Elaborating entity \"cpu_jtag_debug_module_wrapper\" for hierarchy \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\"" {  } { { "cpu.vhd" "the_cpu_jtag_debug_module_wrapper" { Text "C:/altera/Hengdun/LED/cpu.vhd" 3864 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module.vhd 2 1 " "Warning: Using design file cpu_jtag_debug_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_jtag_debug_module-europa " "Info: Found design unit 1: cpu_jtag_debug_module-europa" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "C:/altera/Hengdun/LED/cpu_jtag_debug_module.vhd" 89 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module " "Info: Found entity 1: cpu_jtag_debug_module" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "C:/altera/Hengdun/LED/cpu_jtag_debug_module.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 " "Info: Elaborating entity \"cpu_jtag_debug_module\" for hierarchy \"LCD:inst3\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\"" {  } { { "cpu_jtag_debug_module_wrapper.vhd" "the_cpu_jtag_debug_module1" { Text "C:/altera/Hengdun/LED/cpu_jtag_debug_module_wrapper.vhd" 311 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_mem_s1_arbitrator LCD:inst3\|onchip_mem_s1_arbitrator:the_onchip_mem_s1 " "Info: Elaborating entity \"onchip_mem_s1_arbitrator\" for hierarchy \"LCD:inst3\|onchip_mem_s1_arbitrator:the_onchip_mem_s1\"" {  } { { "LCD.vhd" "the_onchip_mem_s1" { Text "C:/altera/Hengdun/LED/LCD.vhd" 3094 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "onchip_mem.vhd 2 1 " "Warning: Using design file onchip_mem.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 onchip_mem-europa " "Info: Found design unit 1: onchip_mem-europa" {  } { { "onchip_mem.vhd" "" { Text "C:/altera/Hengdun/LED/onchip_mem.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 onchip_mem " "Info: Found entity 1: onchip_mem" {  } { { "onchip_mem.vhd" "" { Text "C:/altera/Hengdun/LED/onchip_mem.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_mem LCD:inst3\|onchip_mem:the_onchip_mem " "Info: Elaborating entity \"onchip_mem\" for hierarchy \"LCD:inst3\|onchip_mem:the_onchip_mem\"" {  } { { "LCD.vhd" "the_onchip_mem" { Text "C:/altera/Hengdun/LED/LCD.vhd" 3132 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram\"" {  } { { "onchip_mem.vhd" "the_altsyncram" { Text "C:/altera/Hengdun/LED/onchip_mem.vhd" 140 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram\"" {  } { { "onchip_mem.vhd" "" { Text "C:/altera/Hengdun/LED/onchip_mem.vhd" 140 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u8b1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u8b1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u8b1 " "Info: Found entity 1: altsyncram_u8b1" {  } { { "db/altsyncram_u8b1.tdf" "" { Text "C:/altera/Hengdun/LED/db/altsyncram_u8b1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u8b1 LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram\|altsyncram_u8b1:auto_generated " "Info: Elaborating entity \"altsyncram_u8b1\" for hierarchy \"LCD:inst3\|onchip_mem:the_onchip_mem\|altsyncram:the_altsyncram\|altsyncram_u8b1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_reset_clk_domain_synch_module LCD:inst3\|LCD_reset_clk_domain_synch_module:LCD_reset_clk_domain_synch " "Info: Elaborating entity \"LCD_reset_clk_domain_synch_module\" for hierarchy \"LCD:inst3\|LCD_reset_clk_domain_synch_module:LCD_reset_clk_domain_synch\"" {  } { { "LCD.vhd" "LCD_reset_clk_domain_synch" { Text "C:/altera/Hengdun/LED/LCD.vhd" 3146 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:inst1 " "Info: Elaborating entity \"led\" for hierarchy \"led:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "C:/altera/Hengdun/LED/Block1.bdf" { { 128 64 184 224 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd 7 2 " "Info: Found 7 design units, including 2 entities, in source file ../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap_lib " "Info: Found design unit 2: sld_signaltap_lib" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 70 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_signaltap_lib-body " "Info: Found design unit 3: sld_signaltap_lib-body" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 75 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_signaltap-rtl " "Info: Found design unit 4: sld_signaltap-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 229 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_signaltap_impl-rtl " "Info: Found design unit 5: sld_signaltap_impl-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 524 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 131 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_signaltap_impl " "Info: Found entity 2: sld_signaltap_impl" {  } { { "../../72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 435 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/sld_ela_control.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../72/quartus/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 129 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 2: sld_ela_basic_multi_level_trigger-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 702 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_basic_multi_level_trigger " "Info: Found entity 2: sld_ela_basic_multi_level_trigger" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 669 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "LPM_SHIFTREG.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 298 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "../../72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 277 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_trigger_flow_mgr-rtl " "Info: Found design unit 1: sld_ela_trigger_flow_mgr-rtl" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_trigger_flow_mgr " "Info: Found entity 1: sld_ela_trigger_flow_mgr" {  } { { "../../72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "C:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/sld_buffer_manager.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../