rom.vhd

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

--QuartusII Version5.0
--MAXII:EPM240T100C5
--BY H.C.H(NNU)
--编译时间:2005-8-10/11:20:29

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity Rom is
port(address: in std_logic_vector(5 downto 0);   
      dout   : out std_logic_vector(7 downto 0) );
end entity Rom;

architecture one of Rom is
    signal temp1:integer range 0 to 255;
    signal temp2:integer range 0 TO 63;
begin
    temp2<=conv_integer(address);
    process(temp2)
    begin
        case temp2 is
            when  0  =>  temp1<=128;
            when  1  =>  temp1<=140;
            when  2  =>  temp1<=153;
            when  3  =>  temp1<=165;
            when  4  =>  temp1<=177;
            when  5  =>  temp1<=188;
            when  6  =>  temp1<=199;
            when  7  =>  temp1<=209;
            when  8  =>  temp1<=219;
            when  9  =>  temp1<=227;
            when  10  =>  temp1<=235;
            when  11  =>  temp1<=241;
            when  12  =>  temp1<=246;
            when  13  =>  temp1<=250;
            when  14  =>  temp1<=253;
            when  15  =>  temp1<=255;
            when  16  =>  temp1<=255;
            when  17  =>  temp1<=254;
            when  18  =>  temp1<=252;
            when  19  =>  temp1<=248;
            when  20  =>  temp1<=244;
            when  21  =>  temp1<=238;
            when  22  =>  temp1<=231;
            when  23  =>  temp1<=223;
            when  24  =>  temp1<=214;
            when  25  =>  temp1<=204;
            when  26  =>  temp1<=194;
            when  27  =>  temp1<=183;
            when  28  =>  temp1<=171;
            when  29  =>  temp1<=159;
            when  30  =>  temp1<=147;
            when  31  =>  temp1<=134;
            when  32  =>  temp1<=121;
            when  33  =>  temp1<=109;
            when  34  =>  temp1<=96;
            when  35  =>  temp1<=84;
            when  36  =>  temp1<=72;
            when  37  =>  temp1<=61;
            when  38  =>  temp1<=51;
            when  39  =>  temp1<=41;
            when  40  =>  temp1<=32;
            when  41  =>  temp1<=24;
            when  42  =>  temp1<=17;
            when  43  =>  temp1<=11;
            when  44  =>  temp1<=7;
            when  45  =>  temp1<=3;
            when  46  =>  temp1<=1;
            when  47  =>  temp1<=0;
            when  48  =>  temp1<=0;
            when  49  =>  temp1<=2;
            when  50  =>  temp1<=5;
            when  51  =>  temp1<=9;
            when  52  =>  temp1<=14;
            when  53  =>  temp1<=20;
            when  54  =>  temp1<=28;
            when  55  =>  temp1<=36;
            when  56  =>  temp1<=46;
            when  57  =>  temp1<=56;
            when  58  =>  temp1<=67;
            when  59  =>  temp1<=78;
            when  60  =>  temp1<=90;
            when  61  =>  temp1<=102;
            when  62  =>  temp1<=115;
            when  63  =>  temp1<=127;
        end case;
    end process;
    Dout<=conv_std_logic_vector(temp1,8);
end architecture one;