led.vhd

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

--Author:Huyugui
--E-mail:[e-mail]
--QQ:190189667


--库定义
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

--实体定义
Entity led is
    Port (clk:  in    std_logic;                   --Input clock
          key1,key2:  in    std_logic_vector(3 downto 0);  --拨动开关
          DDS:  out   std_logic_vector(5 downto 0);
          beep:out    std_logic;                       --蜂鸣器
          d1,d2,d3,d4,d5,d6,d7,d8:out    std_logic;    --接LED灯
          led8,sel,seg:out  std_logic_vector(7 downto 0); --接数码管
          DA1:  out   std_logic_vector(7 downto 0) 
         );
end entity led;


--结构体定义
architecture one of led is
    signal cnt:std_logic_vector(31 downto 0);      --定义一个信号变量对CLOCK进行分频
    signal tmp:std_logic_vector(3 downto 0);
    
begin
    process(clk,key1,key2)
    begin
        if (key1(0)='1') then
           cnt<=(others=>'1');
        elsif Rising_edge(clk) then  --上升沿触发计数
                cnt<=cnt+1;
        end if;

        if(key1(1)='1')  then  
                beep<='1';  --蜂鸣器鸣叫
        else
                beep<='0';
        end if;

        if key1(2)='1' then  
           d3<='1';  --LED3点亮
           d4<='1';  --LED4点亮
        else
           d3<='0';
           d4<='0';
        end if;
        
        if key1(3)='1' then
           d1<='1';  --LED1点亮
           d2<='1';  --LED2点亮
        else
           d1<='0';
           d2<='0';
        end if;
        
        if key2(0)='0' then
           d5<='1'; --LED5点亮
        else
           d5<='0';
        end if;
 
        if key2(1)='0' then
           d6<='1';  --LED6点亮
        else
           d6<='0';
        end if;        
 
        if key2(2)='0' then
           d7<='1';  --LED7点亮
        else
           d7<='0';
        end if; 

        if key2(3)='0' then
           d8<='1';  --LED8点亮
        else
           d8<='0';
        end if; 
    end process;
    DDS<=cnt(5 downto 0);
    DA1<=cnt(7 downto 0);


process(tmp)  --控制4位数码管的数码显示
begin
case tmp is                             
    when "0000" => seg<="00111111";--0
    when "0001" => seg<="00000110";--1
    when "0010" => seg<="01011011";--2
    when "0011" => seg<="01001111";--3
    when "0100" => seg<="01100110";--4
    when "0101" => seg<="01101101";--5
    when "0110" => seg<="01111101";--6
    when "0111" => seg<="00000111";--7
    
   when "1000" => seg<="01111111";--8
   when "1001" => seg<="01101111";--9
   when "1010" => seg<="01110111";--a
   when "1011" => seg<="01111100";--b
   when "1100" => seg<="00111001";--c
   when "1101" => seg<="01011110";--d
   when "1110" => seg<="01111001";
   when "1111" => seg<="01110001";
   when others => seg<="00000000";
end case;
end process;

process(cnt)  --控制1位数码管显示
begin
case cnt(27 downto 24) is
    when "0000" => led8<="00111111";--0
    when "0001" => led8<="00000110";--1
    when "0010" => led8<="01011011";--2
    when "0011" => led8<="01001111";--3
    when "0100" => led8<="01100110";--4
    when "0101" => led8<="01101101";--5
    when "0110" => led8<="01111101";--6
    when "0111" => led8<="00000111";--7 
    when "1000" => led8<="01111111";--8
    when "1001" => led8<="01101111";--9
    when "1010" => led8<="01110111";--a
    when "1011" => led8<="01111100";--b
    when "1100" => led8<="00111001";--c
    when "1101" => led8<="01011110";--d
    when "1110" => led8<="01111001";
    when "1111" => led8<="01110001";
    when others => led8<="00000000";
end case;
end process;

process(cnt)
begin
    case cnt(12 downto 10) is
        when "000"  =>  sel<="11111110";  --控制数码管位数
                        tmp<="0000";      --控制数码管数码显示值
        when "001"  =>  sel<="11111101";
                        tmp<="0001";--tmp<=cnt(7 downto 4);
        when "010"  =>  sel<="11111011";
                        tmp<="0010";--tmp<=cnt(11 downto 8);
        when "011"  =>  sel<="11110111";
                        tmp<="0011";--tmp<=cnt(15 downto 12);
        when "100"  =>  sel<="11101111";
                        tmp<="0100";--tmp<=cnt(19 downto 16);
        when "101"  =>  sel<="11011111";
                        tmp<="0101";--tmp<=cnt(23 downto 20);
        when "110"  =>  sel<="10111111";
                        tmp<="0110";--tmp<=cnt(27 downto 24);
        when "111"  =>  sel<="01111111";
                        tmp<="0111";--tmp<=cnt(31 downto 28);
        when others =>  sel<="01111111";
                        tmp<="1000";--tmp<=cnt(31 downto 28);
    end case;
end process;
  
end architecture one;