ex.map.rpt

cpld系统 EWB Quartus2编译 电子综合设计试验箱程序

+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                     ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------------+
; LED.vhd                          ; yes             ; User VHDL File  ; G:/电子综合设计实验箱测试程序/电子综合设计实验箱测试程序/02_CPLD系统模块/LED.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 49    ;
;     -- Combinational with no register       ; 21    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 28    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 7     ;
;     -- 3 input functions                    ; 14    ;
;     -- 2 input functions                    ; 27    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 23    ;
;     -- arithmetic mode                      ; 26    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 28    ;
;                                             ;       ;
; Total registers                             ; 28    ;
; Total logic cells in carry chains           ; 27    ;
; I/O pins                                    ; 56    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 28    ;
; Total fan-out                               ; 226   ;
; Average fan-out                             ; 2.15  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |led                       ; 49 (49)     ; 28           ; 0           ; 0            ; 0       ; 0         ; 0         ; 56   ; 0            ; 21 (21)      ; 0 (0)             ; 28 (28)          ; 27 (27)         ; 0 (0)      ; |led                ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; cnt[28..31]                           ; Lost fanout        ;
; Total Number of Removed Registers = 4 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 28    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 27    ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; cnt[0]                                 ; 4       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Aug 26 11:36:28 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex -c ex
Info: Found 1 design units, including 1 entities, in source file ex.bdf
    Info: Found entity 1: ex
Info: Found 2 design units, including 1 entities, in source file LED.vhd
    Info: Found design unit 1: led-one
    Info: Found entity 1: led
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "LED" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "led8[7]" is stuck at GND
    Warning (13410): Pin "seg[7]" is stuck at GND
Info: Registers with preset signals will power-up high
Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below.
    Info: Register "cnt[28]" lost all its fanouts during netlist optimizations.
    Info: Register "cnt[29]" lost all its fanouts during netlist optimizations.
    Info: Register "cnt[30]" lost all its fanouts during netlist optimizations.
    Info: Register "cnt[31]" lost all its fanouts during netlist optimizations.
Info: Implemented 105 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 47 output pins
    Info: Implemented 49 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 174 megabytes
    Info: Processing ended: Tue Aug 26 11:36:31 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02