📄 cpld_qq2812.rpt
字号:
4 5 2 0 1 3 a a a a a a a a
7 2 4 6 5 3 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 7/ 7(100%) 8/16( 50%) 30/36( 83%)
B: LC17 - LC32 2/16( 12%) 7/ 7(100%) 1/16( 6%) 14/36( 38%)
C: LC33 - LC48 8/16( 50%) 8/ 8(100%) 2/16( 12%) 24/36( 66%)
D: LC49 - LC64 4/16( 25%) 8/ 8(100%) 2/16( 12%) 19/36( 52%)
E: LC65 - LC80 7/16( 43%) 7/ 7(100%) 1/16( 6%) 21/36( 58%)
F: LC81 - LC96 7/16( 43%) 7/ 7(100%) 2/16( 12%) 27/36( 75%)
G: LC97 - LC112 5/16( 31%) 6/ 6(100%) 1/16( 6%) 18/36( 50%)
H: LC113 - LC128 4/16( 25%) 7/ 7(100%) 1/16( 6%) 15/36( 41%)
I: LC129 - LC144 4/16( 25%) 7/ 7(100%) 3/16( 18%) 14/36( 38%)
J: LC145 - LC160 14/16( 87%) 6/ 6(100%) 7/16( 43%) 32/36( 88%)
K: LC161 - LC176 3/16( 18%) 7/ 7(100%) 1/16( 6%) 13/36( 36%)
L: LC177 - LC192 4/16( 25%) 7/ 7(100%) 0/16( 0%) 6/36( 16%)
M: LC193 - LC208 1/16( 6%) 8/ 8(100%) 2/16( 12%) 10/36( 27%)
N: LC209 - LC224 1/16( 6%) 7/ 7(100%) 2/16( 12%) 12/36( 33%)
O: LC225 - LC240 1/16( 6%) 6/ 6(100%) 0/16( 0%) 2/36( 5%)
P: LC241 - LC256 7/16( 43%) 7/ 7(100%) 4/16( 25%) 24/36( 66%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 112/112 (100%)
Total logic cells used: 82/256 ( 32%)
Total shareable expanders used: 25/256 ( 9%)
Total Turbo logic cells used: 82/256 ( 32%)
Total shareable expanders not available (n/a): 12/256 ( 4%)
Average fan-in: 8.31
Total fan-in: 682
Total input pins required: 51
Total output pins required: 49
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 82
Total flipflops required: 48
Total product terms required: 274
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 17
Synthesized logic cells: 19/ 256 ( 7%)
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
139 (16) (A) INPUT 0 0 0 0 0 1 0 CANRX_1
49 (120) (H) INPUT 0 0 0 0 0 1 0 CANTX
62 (187) (L) INPUT 0 0 0 0 0 0 0 CLKOUT
65 (192) (L) INPUT 0 0 0 0 0 43 15 CS1
44 (49) (D) INPUT 0 0 0 0 0 43 18 DSP_Add0
45 (128) (H) INPUT 0 0 0 0 0 43 18 DSP_Add1
43 (51) (D) INPUT 0 0 0 0 0 43 18 DSP_Add2
46 (125) (H) INPUT 0 0 0 0 0 43 18 DSP_Add3
41 (54) (D) INPUT 0 0 0 0 0 43 18 DSP_Add4
42 (53) (D) INPUT 0 0 0 0 0 43 18 DSP_Add5
69 246 P BIDIR 1 0 0 9 4 0 4 DSP_Data0 (:286)
68 245 P BIDIR 1 0 0 9 4 0 4 DSP_Data1 (:285)
54 115 H BIDIR 0 0 0 1 2 0 2 DSP_Data2 (:284)
67 243 P BIDIR 0 0 0 1 2 0 2 DSP_Data3 (:283)
60 184 L BIDIR 0 0 0 1 2 0 2 DSP_Data4 (:282)
66 241 P BIDIR 0 0 0 1 1 0 1 DSP_Data5 (:281)
61 185 L BIDIR 0 0 0 1 1 0 1 DSP_Data6 (:280)
53 117 H BIDIR 0 0 0 1 1 0 1 DSP_Data7 (:279)
113 (208) (M) INPUT 0 0 0 0 0 1 1 EXINT0
116 (131) (I) INPUT 0 0 0 0 0 1 1 EXINT1
117 (133) (I) INPUT 0 0 0 0 0 1 1 EXINT2
118 (136) (I) INPUT 0 0 0 0 0 1 1 EXINT3
140 (14) (A) INPUT 0 0 0 0 0 1 1 EXINT4
79 (235) (O) INPUT 0 0 0 0 0 0 2 FIFO_EMPTY
80 (237) (O) INPUT 0 0 0 0 0 0 2 FIFO_FULL
81 (240) (O) INPUT 0 0 0 0 0 0 1 FIFO_PROG
82 (163) (K) INPUT 0 0 0 0 0 0 0 IFCLK
110 (201) (M) INPUT 0 0 0 0 0 1 1 IN0
109 (200) (M) INPUT 0 0 0 0 0 1 1 IN1
108 (197) (M) INPUT 0 0 0 0 0 0 1 IN2
107 (195) (M) INPUT 0 0 0 0 0 0 1 IN3
106 (193) (M) INPUT 0 0 0 0 0 0 1 IN4
103 (221) (N) INPUT 0 0 0 0 0 0 1 IN5
102 (219) (N) INPUT 0 0 0 0 0 0 1 IN6
101 (217) (N) INPUT 0 0 0 0 0 0 1 IN7
100 (216) (N) INPUT 0 0 0 0 0 0 2 IN8
99 (213) (N) INPUT 0 0 0 0 0 0 2 IN9
98 (211) (N) INPUT 0 0 0 0 0 0 1 IN10
97 (160) (J) INPUT 0 0 0 0 0 0 1 IN11
96 (157) (J) INPUT 0 0 0 0 0 0 1 IN12
93 (153) (J) INPUT 0 0 0 0 0 0 1 IN13
92 (152) (J) INPUT 0 0 0 0 0 0 1 IN14
91 (149) (J) INPUT 0 0 0 0 0 0 1 IN15
141 (13) (A) INPUT 0 0 0 0 0 1 0 Key0
7 (25) (B) INPUT 0 0 0 0 0 1 0 Key1
8 (24) (B) INPUT 0 0 0 0 0 1 0 Key2
6 (27) (B) INPUT 0 0 0 0 0 1 0 Key3
5 (29) (B) INPUT 0 0 0 0 0 1 0 Key4
2 (3) (A) INPUT 0 0 0 0 0 1 0 Key5
1 (5) (A) INPUT 0 0 0 0 0 1 0 Key6
143 (6) (A) INPUT 0 0 0 0 0 1 0 Key7
111 (203) (M) INPUT 0 0 0 0 0 1 2 NMI1
112 (206) (M) INPUT 0 0 0 0 0 1 2 NMI2
78 (233) (O) INPUT 0 0 0 0 0 0 2 PA0
75 (229) (O) INPUT 0 0 0 0 0 0 2 PA1
63 (189) (L) INPUT 0 0 0 0 0 10 1 RD
84 (168) (K) INPUT 0 0 0 0 0 0 0 RXB
86 (169) (K) INPUT 0 0 0 0 0 1 0 TXB
70 (249) (P) INPUT 0 0 0 0 0 41 0 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
90 147 J FF t 1 1 0 9 1 1 0 ACICS (:607)
47 123 H FF t 1 0 0 9 1 1 0 BUZZER (:324)
48 121 H OUTPUT t 0 0 0 1 0 0 0 CANRX
138 69 E OUTPUT t 0 0 0 1 0 0 0 CANTX_1
69 246 P TRI/FF t 1 0 0 9 4 0 4 DSP_Data0 (:286)
68 245 P TRI/FF t 1 0 0 9 4 0 4 DSP_Data1 (:285)
54 115 H TRI/FF t 0 0 0 1 2 0 2 DSP_Data2 (:284)
67 243 P TRI/FF t 0 0 0 1 2 0 2 DSP_Data3 (:283)
60 184 L TRI/FF t 0 0 0 1 2 0 2 DSP_Data4 (:282)
66 241 P TRI/FF t 0 0 0 1 1 0 1 DSP_Data5 (:281)
61 185 L TRI/FF t 0 0 0 1 1 0 1 DSP_Data6 (:280)
53 117 H TRI/FF t 0 0 0 1 1 0 1 DSP_Data7 (:279)
120 139 I FF t 1 0 0 9 1 1 0 E (:412)
39 59 D OUTPUT t 0 0 0 5 0 0 5 INT1
121 141 I FF t 1 1 0 9 1 1 0 LCD_Data0 (:470)
122 144 I FF t 1 1 0 9 1 1 0 LCD_Data1 (:469)
131 80 E FF t 1 1 0 9 1 1 0 LCD_Data2 (:468)
132 78 E FF t 1 1 0 9 1 1 0 LCD_Data3 (:467)
133 77 E FF t 1 1 0 9 1 1 0 LCD_Data4 (:466)
134 75 E FF t 1 1 0 9 1 1 0 LCD_Data5 (:465)
136 73 E FF t 1 1 0 9 1 1 0 LCD_Data6 (:464)
137 72 E FF t 1 1 0 9 1 1 0 LCD_Data7 (:463)
142 11 A FF t 1 1 0 10 1 1 0 LED0 (:383)
9 21 B FF t 1 1 0 10 1 1 0 LED1 (:382)
10 19 B FF t 1 1 0 10 1 1 0 LED2 (:381)
11 96 F FF t 1 1 0 10 1 1 0 LED3 (:380)
12 93 F FF t 1 1 0 10 1 1 0 LED4 (:379)
14 91 F FF t 1 1 0 10 1 1 0 LED5 (:378)
15 89 F FF t 1 1 0 10 1 1 0 LED6 (:377)
16 88 F FF t 1 1 0 10 1 1 0 LED7 (:376)
40 56 D OUTPUT t ! 0 0 0 2 0 0 2 NMI
18 85 F FF t 1 1 0 9 1 1 0 OUT0 (:722)
19 83 F FF t 1 1 0 9 1 1 0 OUT1 (:721)
21 109 G FF t 1 1 0 9 1 1 0 OUT2 (:720)
22 107 G FF t 1 1 0 9 1 1 0 OUT3 (:719)
23 105 G FF t 1 1 0 9 1 1 0 OUT4 (:718)
25 104 G FF t 1 1 0 9 1 1 0 OUT5 (:717)
27 99 G FF t 1 1 0 9 1 1 0 OUT6 (:716)
28 48 C FF t 1 1 0 9 1 1 0 OUT7 (:715)
29 45 C FF t 1 1 0 9 1 1 0 OUT8 (:714)
30 43 C FF t 1 1 0 9 1 1 0 OUT9 (:713)
31 41 C FF t 1 1 0 9 1 1 0 OUT10 (:712)
32 40 C FF t 1 1 0 9 1 1 0 OUT11 (:711)
34 37 C FF t 1 1 0 9 1 1 0 OUT12 (:710)
35 35 C FF t 1 1 0 9 1 1 0 OUT13 (:709)
36 33 C FF t 1 1 0 9 1 1 0 OUT14 (:708)
37 64 D FF t 1 1 0 9 1 1 0 OUT15 (:707)
72 256 P FF t 1 0 0 9 1 1 0 PATEND (:519)
119 137 I FF t 1 0 0 9 1 1 0 RS (:427)
87 171 K FF t 1 1 0 9 1 1 0 SICLK (:623)
88 173 K FF t 1 1 0 9 1 1 0 SIDIN (:615)
71 253 P OUTPUT t ! 0 0 0 7 0 3 0 SLCS
74 227 O OUTPUT s t ! 0 0 0 1 1 0 0 SLOE
55 179 L OUTPUT t ! 0 0 0 1 1 0 0 SLRD
56 181 L OUTPUT t ! 0 0 0 1 1 0 0 SLWR
38 61 D FF t 1 0 0 9 1 1 0 SPI_CS (:592)
83 165 K OUTPUT t 0 0 0 1 0 0 0 TXB1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\code\cpld_qq2812\cpld_qq2812.rpt
cpld_qq2812
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 155 J OR2 t 0 0 0 1 2 0 2 :182
- 151 J OR2 t 0 0 0 1 2 0 2 :183
- 150 J OR2 t 0 0 0 1 2 0 2 :184
(92) 152 J OR2 t 0 0 0 1 2 0 3 :185
- 10 A OR2 t 0 0 0 1 2 0 3 :186
- 12 A OR2 t 0 0 0 2 2 0 3 :212
- 9 A OR2 t 0 0 0 2 2 0 3 :216
(96) 157 J OR2 s t ! 0 0 0 6 1 1 0 ~273~1
- 159 J OR2 s t ! 0 0 0 6 1 1 0 ~273~2
(91) 149 J OR2 s t ! 0 0 0 6 1 1 0 ~274~1
(143) 6 A OR2 s t 2 1 1 9 1 1 0 DSP_Data_reg7~1 (~279~1)
- 196 M OR2 s t 2 1 1 9 1 1 0 DSP_Data_reg6~1 (~280~1)
- 4 A OR2 s t 2 1 1 9 1 1 0 DSP_Data_reg5~1 (~281~1)
- 158 J OR2 s t 1 0 0 9 2 1 0 DSP_Data_reg4~1 (~282~1)
- 156 J OR2 s t 1 0 0 9 2 1 0 DSP_Data_reg3~1 (~283~1)
- 212 N OR2 s t 2 0 1 10 2 1 0 DSP_Data_reg2~1 (~284~1)
- 146 J OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg1~1 (~285~1)
- 154 J OR2 s t 1 0 1 9 3 1 0 DSP_Data_reg1~2 (~285~2)
- 148 J OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg1~3 (~285~3)
- 145 J OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg1~4 (~285~4)
(2) 3 A OR2 s t 1 0 1 8 1 1 0 DSP_Data_reg0~1 (~286~1)
- 2 A OR2 s t 1 0 1 9 3 1 0 DSP_Data_reg0~2 (~286~2)
(141) 13 A OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg0~3 (~286~3)
- 1 A OR2 s t 1 0 1 9 2 1 0 DSP_Data_reg0~4 (~286~4)
- 248 P SOFT s t 1 0 0 8 0 0 0 DSP_Data_reg0~5 (~286~5)
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