📄 scan8.vhd
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity scan8 is port (clk : in std_logic; a,b,c,d,e,f,g,h : in std_logic_vector(7 downto 0); pa,pb,pc,pd,pe,pf,pg,ph : out std_logic; mux_out :out std_logic_vector(7 downto 0) );end scan8;architecture arch of scan8 is signal sel : std_logic_vector(2 downto 0):="000";begin process(clk,a,b,c,d,e,f,g,h) begin --if rst='1' then sel<="000"; if rising_edge(clk) then --if sel = "110" then -- sel<= "000"; -- mux_out <= a; -- pa<='0';pb<='1';pc<='1';pd<='1';pe<='1';pf<='1'; -- else -- sel<=sel + "001"; -- end if; case sel is when "000" => mux_out <= a; pa<='0';pb<='1';pc<='1'; pd<='1';pe<='1';pf<='1';pg<='1';ph<='1'; when "001" => mux_out <= b; pa<='1';pb<='0';pc<='1'; pd<='1';pe<='1';pf<='1';pg<='1';ph<='1'; when "010" => mux_out <= c; pa<='1';pb<='1';pc<='0'; pd<='1';pe<='1';pf<='1';pg<='1';ph<='1'; when "011" => mux_out <= d; pa<='1';pb<='1';pc<='1'; pd<='0';pe<='1';pf<='1';pg<='1';ph<='1'; when "100" => mux_out <= e; pa<='1';pb<='1';pc<='1'; pd<='1';pe<='0';pf<='1';pg<='1';ph<='1'; when "101" => mux_out <= f; pa<='1';pb<='1';pc<='1'; pd<='1';pe<='1';pf<='0';pg<='1';ph<='1'; when "110" => mux_out <= g; pa<='1';pb<='1';pc<='1'; pd<='1';pe<='1';pf<='1';pg<='0';ph<='1'; when "111" => mux_out <= h; pa<='1';pb<='1';pc<='1'; pd<='1';pe<='1';pf<='1';pg<='1';ph<='0'; when others => mux_out <= "11111111"; pa<='1';pb<='1';pc<='1'; pd<='1';pe<='1';pf<='1';pg<='1';ph<='1'; end case; sel<=sel + "001"; end if; end process;end arch;
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