div_clock.vhd

在FPGA上实现的出租车计价器VHDL源代码

Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity div_clock is
  Port( clk: in std_logic;--from system clock
        f50hz: out std_logic;-- 500Hz output signal
		  f10hz: out std_logic;-- 10Hz output signal
		  f5hz: out std_logic;-- 5Hz output signal
        f1hz: out std_logic);-- 1Hz output signal
end div_clock;
architecture arch of div_clock is
  signal clk1,clk2,CLK3,clk4:std_logic;
    begin
    pulse0:process(clk)
     variable count1:integer range 0 to 100000;
     variable count2:integer range 0 to 500;
     variable count3:integer range 0 to 50;
     variable count4:integer range 0 to 100;     
      begin
        if clk'event and clk='1' then 
           count1:=count1+1;
           if count1=50000 then clk1<='1';                 
             elsif count1=100000 then 
             clk1<='0';
             count1:=0;
           end if; 
        end if;
        f50hz<=clk1;
        if clk1'event and clk1='1' then 
           count2:=count2+1;
           if count2=250 then 
             clk2<='1';                 
             elsif count2=500 then 
             clk2<='0';
             count2:=0;
           end if; 
        end if;
        f1hz<=clk2;
		  if clk1'event and clk1='1' then 
           count3:=count2+1;
           if count3=25 then 
             clk3<='1';                 
             elsif count3=50 then 
             clk3<='0';
             count3:=0;
           end if; 
        end if;
        f10hz<=clk3;
		  if clk1'event and clk1='1' then 
           count4:=count2+1;
           if count4=25 then 
             clk4<='1';                 
             elsif count4=50 then 
             clk4<='0';
             count4:=0;
           end if; 
        end if;
        f5hz<=clk4;
    end process pulse0;
end arch;