taxi_top.vhd

在FPGA上实现的出租车计价器VHDL源代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_pkg.all;
entity taxi_top is
  port(--key_sel: in std_logic;
       clk: in std_logic;		
		 --key_statr,key_stop: in std_logic;
		 start,waiting: in std_logic;
		 Q : out std_logic_vector(3 downto 0);
		 --spkout: out std_logic;		 
		 seg8: out std_logic_vector(7 downto 0);
		 p1,p2,p3,p4,p5,p6,p7,p8: out std_logic);
end taxi_top;

architecture Behavioral of taxi_top is
  signal hz1,hz500,hz10,hz5:std_logic;
  --signal start,waiting: std_logic; 
  signal c3,c2,c1,c0: std_logic_vector(3 downto 0);
  signal k2,k1,k0: std_logic_vector(3 downto 0);
  signal m1,m0: std_logic_vector(3 downto 0);
  signal led7,led6,led5,led4,led3,led2,led1,led0: std_logic_vector(7 downto 0);    
begin
  u0: div_clock port map(clk=>clk,f50hz=>hz500,f10hz=>hz10,f5hz=>hz5,f1hz=>hz1);
  --u1: keydown port map (keyin=>key_statr,clk=>hz5,keyout=>start);
  --u2: keydown port map (keyin=>key_stop,clk=>hz5,keyout=>waiting);
  u3: taxi port map ( f_1=>hz1,clk_50=>hz500,f_in=>hz10,clk=>clk,start=> start,waiting=>waiting,   
       cha3=>c3,cha2=>c2,cha1=>c1,cha0=>c0,km2=>k2, km1=>k1,km0=>k0,min1=>m1,min0=>m0);
scan_display:block
begin
  u4: bin2led port map(bin=>c3,led=>led7);
  u5: bin2led port map(bin=>c2,led=>led6);
  u6: bin2led port map(bin=>c1,led=>led5);
  u7: bin2led port map(bin=>c0,led=>led4);
  u8: bin2led port map(bin=>k2,led=>led3);
  u9: bin2led port map(bin=>k1,led=>led2);
  u10:bin2led port map(bin=>k0,led=>led1);
  u11:bin2led port map(bin=>m1,led=>led0);
  Q<=m0;
  u12:scan8 port map(  clk=>hz500,a=>led7,b=>led6,c=>led5,d=>led4,
                       e=>led3,f=>led2,g=>led1,h=>led0,                       
							  mux_out=>seg8,pa=>p1,pb=>p2,pc=>p3,pd=>p4,
							  pe=>p5,pf=>p6,pg=>p7,ph=>p8);
end block scan_display;     
end Behavioral;