my_pkg.vhd

来自「在FPGA上实现的出租车计价器VHDL源代码」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
  component div_clock
  port(clk: in std_logic;
       f50hz: out std_logic;
		 f10hz: out std_logic;-- 5Hz output signal
		 f5hz: out std_logic;
       f1hz: out std_logic);
  end component;  
component scan8 is
  port (clk : in std_logic;
        a,b,c,d,e,f,g,h : in std_logic_vector(7 downto 0);
		  pa,pb,pc,pd,pe,pf,pg,ph : out std_logic;
		  mux_out: out std_logic_vector(7 downto 0)  );
end component;
component bin2led is
  port (bin : in std_logic_vector(3 downto 0);
        led : out std_logic_vector(7 downto 0) );
end component;
--component keydown is
  --  port(keyin    :in std_logic;
    --     clk      :in std_logic;
         --clk1     :in std_logic;
  --       keyout   :out std_logic);
--end component;
component taxi is
port ( f_1,clk_50,f_in,clk:in std_logic;                                                  
       start :in std_logic;                               
       waiting:in std_logic;                                             
       cha3,cha2,cha1,cha0:out std_logic_vector(3 downto 0);
       km2, km1,km0:out std_logic_vector(3 downto 0);               
       min1,min0: out std_logic_vector(3 downto 0));       
end component;

end my_pkg;