📄 qam029old7.c
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//#define SERIAL_MODE
//#define DCF_8710
/************************************************************************
COPYRIGHT (C) HUST E&I HDTV Group 1999
Source file name : st_tuner.c
Author : H.B.
Zjz
Based on original work by:
Leszek Dymaczewski
Mariano Bona,
Thierry Abraham,
T.H.Thillai Rajan
----------------------------*
Thanks to : Wyl
Brenda
File description:
Prototype driver for STV0297
Date Modification Initials
---- ------------ --------
24-12-1999 Created H.B.
************************************************************************/
#include "appldef.h"
#include "sti2c.h"
#include "dbaseiterface.h"
/*
#include "qam297.h"
*/
/*#define TUNER_TEMIC_4707PH5*/
#define TUNER_SHARP_CASD19E04
#define MAX_ACQUISITION_ATTEMPT_BEFORE_IQ_INVERT 3
/*#ifdef TESTTOOL_PRESENT
#define QAM_DEBUG
#endif*/
// #define QAM_DEBUG
#ifdef QAM_DEBUG
#define QAM_DEBUG_CODE(__code__) __code__
#else
#define QAM_DEBUG_CODE(__code__)
#endif
#define DUMMY_CODE \
{\
int __HuBo__Birthday__; \
__HuBo__Birthday__=1104;\
}
#define LINK_CLOCK_FREQUENCY 28900 /* KHz */
/* fang020119 */
static unsigned char LockIndicator=0;
static unsigned int NoSignalCount=0;
static unsigned char MsgFlag=0;
static unsigned char s_AgcNoSignal=0;
#define QAM16 0x00
#define QAM32 0x10
#define QAM64 0x40
#define QAM128 0x20
#define QAM256 0x30
STI2C_Handle_t I2CDemodHandle;
STI2C_Handle_t I2CTunerHandle;
#define i2c_ssc0 0x00
#define TUNER_SOFTWARE_UPDATE_ID "0.0Beta"
typedef enum
{
TUNER_IDLE,
SIGNAL_DETECTION,
ACQUISITION,
MONITOR_TUNING
} tuner_state_t;
#define ACQUISITION_TIMEOUT 300/*zjz500*/
#define LOCK_TEST_INTERVAL 50
#define MONITOR_LOCK_TEST_INTERVAL 100
#define LINKIC_DEV 0x38 /* I2C slave address for LINKIC (STv0297) */
#define INITIAL_SWEEP_RATE 718 //718 /* 1/1000 Fs 3400*/
/* fang020118 ?? */
static int globalInitFrequencyOffser=-70;//-20;//-70;/*-54*/ /*/xiejiang/*/
#define INITIAL_FREQUENCY_OFFSET globalInitFrequencyOffser /*(-54)for>=520Mhz (-35)for<520MHz */ /* KHz */
#define INITIAL_SPECTRUM_INVERSION 0
extern const int TUNER_PROCESS_PRIORITY;
extern const int TUNER_PROCESS_STACK_SIZE;
void Driv0297CNEstimatorInit(void);
#define TUNER_SETTLING_TIME 100 /* Settling time for freq set */
/* frequency factors */
#ifdef TUNER_SHARP_CASD19E04
#define TUNER_DEV 0xC0
#define TUNER_IF 36000
#define TUNER_STEP 62.5
#define LOW_BAND_UPPER_BOUNDARY 179650 /* KHz */
#define MID_BAND_UPPER_BOUNDARY 454650 /* KHz */
#define LOW_BAND 0x04
#define MID_BAND 0x02
#define HIGH_BAND 0x81
#define CHARGE_PUMP_ON 0xce
#define CHARGE_PUMP_OFF 0x8e
#endif
#ifdef TUNER_TEMIC_4707PH5
#define TUNER_DEV 0xC0
#define TUNER_IF 36125
#define TUNER_STEP 62.5
#define LOW_BAND_UPPER_BOUNDARY 179650 /* KHz */
#define MID_BAND_UPPER_BOUNDARY 454650 /* KHz */
#define LOW_BAND 0x02
#define MID_BAND 0x04
#define HIGH_BAND 0x02
#define CHARGE_PUMP_ON 0xce
#define CHARGE_PUMP_OFF 0x8e
#endif
/* Registers addresses definition */
/* Equalizer - Constellation Quality Estimator */
#define EQU_0 0x00 /**/
#define EQU_1 0x01 /**/
#define EQU_2 0x02 /**/
#define EQU_3 0x03 /**/
#define EQU_4 0x04 /**/
#define EQU_5 0x05 /**/
#define EQU_6 0x06 /**/
#define EQU_7 0x07 /**/
#define EQU_8 0x08 /**/
/* Quadrature Demodulator */
#define INITDEM_0 0x20 /**/
#define INITDEM_1 0x21 /**/
#define INITDEM_2 0x22 /**/
#define INITDEM_3 0x23 /**/
#define INITDEM_4 0x24 /**/
#define INITDEM_5 0x25 /**/
/* Analog AGCs - A/D Overflow Monitor - General Purpose PWM */
#define DELAGC_0 0x30 /**/
#define DELAGC_1 0x31 /**/
#define DELAGC_2 0x32 /**/
#define DELAGC_3 0x33 /**/
#define DELAGC_4 0x34 /**/
#define DELAGC_5 0x35 /**/
#define DELAGC_6 0x36 /**/
#define DELAGC_7 0x37 /**/
#define DELAGC_8 0x38 /**/
#define WBAGC_0 0x40 /**/
#define WBAGC_1 0x41 /**/
#define WBAGC_2 0x42 /**/
#define WBAGC_3 0x43 /**/
#define WBAGC_4 0x44 /**/
#define WBAGC_5 0x45 /**/
#define WBAGC_6 0x46 /**/
#define WBAGC_9 0x49 /**/
#define WBAGC_10 0x4a /**/
#define WBAGC_11 0x4b /**/
/* Symbol Timing Recovery Loop */
#define STLOOP_2 0x52 /**/
#define STLOOP_3 0x53 /**/
#define STLOOP_5 0x55 /**/
#define STLOOP_6 0x56 /**/
#define STLOOP_7 0x57 /**/
#define STLOOP_8 0x58 /**/
#define STLOOP_9 0x59 /**/
#define STLOOP_10 0x5a /**/
#define STLOOP_11 0x5b /**/
/* Carrier Recovery Loop */
#define CRL_0 0x60 /**/
#define CRL_1 0x61 /**/
#define CRL_2 0x62 /**/
#define CRL_3 0x63 /**/
#define CRL_4 0x64 /**/
#define CRL_5 0x65 /**/
#define CRL_6 0x66 /**/
#define CRL_7 0x67 /**/
#define CRL_8 0x68 /**/
#define CRL_9 0x69 /**/
#define CRL_10 0x6a /**/
#define CRL_11 0x6b /**/
/* Post Filter Digital AGC */
#define PMFAGC_0 0x70 /**/
#define PMFAGC_1 0x71 /**/
#define PMFAGC_2 0x72 /**/
#define PMFAGC_3 0x73 /**/
#define PMFAGC_4 0x74 /**/
/* Configuration and Control */
#define CTRL_0 0x80 /**/
#define CTRL_1 0x81 /**/
#define CTRL_2 0x82 /**/
#define CTRL_3 0x83 /**/
#define CTRL_4 0x84 /**/
#define CTRL_5 0x85 /**/
#define CTRL_6 0x86 /**/
#define CTRL_7 0x87 /**/
#define CTRL_8 0x88 /**/
#define CTRL_9 0x89 /**/
/* Deinterleaver Sync Detector */
#define DEINT_SYNC_0 0x90 /**/
#define DEINT_SYNC_1 0x91 /**/
/* Integrated BER Tester */
#define BERT_0 0xa0 /**/
#define BERT_1 0xa1 /**/
#define BERT_2 0xa2 /**/
/* Deinterleaver */
#define DEINT_0 0xb0 /**/
#define DEINT_1 0xb1 /**/
#define DEINT_2 0xb2 /**/
#define DEINT_3 0xb3 /**/
/* Output Formatter */
#define OUTFORMAT_0 0xc0 /**/
#define OUTFORMAT_1 0xc1 /**/
#define OUTFORMAT_2 0xc2 /**/
/* Reed-Solomon - Descrambler Sync Detector - Descrambler */
#define RS_DESC_0 0xd0 /**/
#define RS_DESC_1 0xd1 /**/
#define RS_DESC_2 0xd2 /**/
#define RS_DESC_3 0xd3 /**/
#define RS_DESC_4 0xd4 /**/
#define RS_DESC_5 0xd5 /**/
#define RS_DESC_14 0xde /**/
#define RS_DESC_15 0xdf /**/
/* Register Initial Value */
#define INIT_RESERVED 0x00
#define INIT_RESET_VALUE(__value__) __value__
#define INIT_NOT_NEED 0x00
#define INIT_EQU_0 QAM64 | 0x08
#define INIT_EQU_1 0x58
#define INIT_EQU_2 INIT_RESERVED
#define INIT_EQU_3 0x00
#define INIT_EQU_4 INIT_NOT_NEED
#define INIT_EQU_5 INIT_RESERVED
#define INIT_EQU_6 INIT_RESERVED
#define INIT_EQU_7 INIT_NOT_NEED
#define INIT_EQU_8 INIT_NOT_NEED
#define INIT_INITDEM_0 0xeb /*0x00**/
#define INIT_INITDEM_1 0x3f /*0x40 7.23MHz */
#define INIT_INITDEM_2 0x50 /**/
#define INIT_INITDEM_3 0x00 /**/
#define INIT_INITDEM_4 0x00 /**/
#define INIT_INITDEM_5 0x08 /**/
#define INIT_DELAGC_0 0xff /*IF AGC2 max*/
#define INIT_DELAGC_1 0x00 //57 /*IF AGC2 min57*/
#define INIT_DELAGC_2 0xff /* 0x55 */ /*0xff*/ /*zjz0x50*/ /*Tuner AGC1 max*/
#define INIT_DELAGC_3 0x00 /*Tuner AGC1 min*/
#define INIT_DELAGC_4 0x52 //32 /* 0x7A */ /*0x52*/ /*0x01*/ /*[7..5]:a,[4..3]:b,[2..0]:c slop[AGC1]/slop[AGC2]=(2**a+2**b)/2**c */
int gloabAGC2Threshould=0x50;
#define INIT_DELAGC_5 0x7f/*from xiejiang 0x50*//*gloabAGC2Threshould*/ /*zjz0xff*/ /* Tuner AGC2 threshould */
#define INIT_DELAGC_6 0x80 /*0xa8*/ /*0x80*/ /*0x80最高位为一才把AGC1打开，现在关闭*/
#define INIT_DELAGC_7 0x00/*0x7f*/ /**/
#define INIT_DELAGC_8 INIT_NOT_NEED
#define INIT_WBAGC_0 0x18 /* 0x18 zjz0x18Suggested : 0x1c */
#define INIT_WBAGC_1 0x00/*0x10 INIT_NOT_NEED应该为零*/
#define INIT_WBAGC_2 0x28/*0x28 应为2A*/
#define INIT_WBAGC_3 0x30/*0x10*/ /**/
#define INIT_WBAGC_4 0xff /**/
#define INIT_WBAGC_5 INIT_NOT_NEED
#define INIT_WBAGC_6 INIT_NOT_NEED
#define INIT_WBAGC_9 0x04 /**/
#define INIT_WBAGC_10 INIT_NOT_NEED
#define INIT_WBAGC_11 INIT_NOT_NEED
#define INIT_STLOOP_2 0x60 /*0x30*/
#define INIT_STLOOP_3 0x08 /**/
#define INIT_STLOOP_5 INIT_NOT_NEED
#define INIT_STLOOP_6 INIT_NOT_NEED
#define INIT_STLOOP_7 INIT_NOT_NEED
#define INIT_STLOOP_8 INIT_NOT_NEED
#define INIT_STLOOP_9 0x08 /**/
#define INIT_STLOOP_10 0x5e /**/
#define INIT_STLOOP_11 0x05 /**/
#define INIT_CRL_0 0x05/*0x1c*/ /**/
#define INIT_CRL_1 0x49 /**/
#define INIT_CRL_2 0x0a /**/
#define INIT_CRL_3 INIT_NOT_NEED
#define INIT_CRL_4 INIT_NOT_NEED
#define INIT_CRL_5 INIT_NOT_NEED
#define INIT_CRL_6 0x9c/*0xd9*/ /**/
#define INIT_CRL_7 0x60/*0x69*/ /**/
#define INIT_CRL_8 0xc0/*0x000xe4*/ /**/
#define INIT_CRL_9 0x00/*0x0f*/ /**/
#define INIT_CRL_10 0x03 /**/
#define INIT_CRL_11 0xff/*INIT_NOT_NEED*/
#define INIT_PMFAGC_0 0xff /**/
#define INIT_PMFAGC_1 0x04 /**/
#define INIT_PMFAGC_2 INIT_NOT_NEED
#define INIT_PMFAGC_3 INIT_NOT_NEED
#define INIT_PMFAGC_4 INIT_NOT_NEED
#define INIT_CTRL_0 INIT_NOT_NEED
#define INIT_CTRL_1 INIT_NOT_NEED
#define INIT_CTRL_2 INIT_RESET_VALUE(0x00)
#define INIT_CTRL_3 INIT_RESET_VALUE(0x00)
#define INIT_CTRL_4 0x22/*0x22 zjz*/
#define INIT_CTRL_5 INIT_RESET_VALUE(0x00)
#define INIT_CTRL_6 0x40 /*0x60*/
#define INIT_CTRL_7 0x6b /*0x60*/
#define INIT_CTRL_8 0x10/*0x00*/ /**/
#define INIT_CTRL_9 INIT_RESET_VALUE(0x00)
#define INIT_DEINT_SYNC_0 INIT_RESET_VALUE(0x01)
#define INIT_DEINT_SYNC_1 0x04 /**/
#define INIT_BERT_0 INIT_NOT_NEED
#define INIT_BERT_1 INIT_NOT_NEED
#define INIT_BERT_2 INIT_NOT_NEED
#define INIT_DEINT_0 INIT_RESET_VALUE(0x91)
#define INIT_DEINT_1 INIT_RESET_VALUE(0x0b)
#define INIT_DEINT_2 INIT_RESERVED
#define INIT_DEINT_3 INIT_RESERVED
//#define INIT_OUTFORMAT_0 0x5f/*0x5b for parallel output*//* 0x5f for serial output*/
#ifdef SERIAL_MODE
#define INIT_OUTFORMAT_0 0x5f /*0x5b for parallel output*//* 0x5f for serial output*/
#else
#define INIT_OUTFORMAT_0 0x4b /*0x5b for parallel output (in 5518 parallel interface is 0x4b)*//* 0x5f for serial output*/
#endif
#define INIT_OUTFORMAT_1 INIT_RESET_VALUE(0x00)
#define INIT_OUTFORMAT_2 0x00 /**/
#define INIT_RS_DESC_0 INIT_NOT_NEED
#define INIT_RS_DESC_1 INIT_NOT_NEED
#define INIT_RS_DESC_2 INIT_NOT_NEED
#define INIT_RS_DESC_3 INIT_NOT_NEED
#define INIT_RS_DESC_4 INIT_NOT_NEED
#define INIT_RS_DESC_5 INIT_NOT_NEED
#define INIT_RS_DESC_14 INIT_RESET_VALUE(0x00)
#define INIT_RS_DESC_15 INIT_RESET_VALUE(0x00)
/* I2c enable pin pio0.7 */
#define TUNER_I2C_ENABLE_PIO_ADDRESS PIO_0_BASE_ADDRESS
#define TUNER_I2C_ENABLE_PIN 0x80
#define ENABLE_TUNER_I2C \
* ( ( volatile BYTE * ) ( TUNER_I2C_ENABLE_PIO_ADDRESS + PIO_SET_OFFSET ) ) = TUNER_I2C_ENABLE_PIN;
#define DISABLE_TUNER_I2C \
* ( ( volatile BYTE * ) ( TUNER_I2C_ENABLE_PIO_ADDRESS + PIO_CLR_OFFSET ) ) = TUNER_I2C_ENABLE_PIN;
/* change frequency in KHz to tuner LSB values */
#define CHANGE_KHZ_TO_LSB(__freq__) \
( ( ( float ) __freq__ + ( float ) TUNER_IF ) / ( float ) TUNER_STEP )
/*
* force tuner_state which will not verify what is the current state.
* this will be invoked only if the new_tune_req is received
*/
#define FORCE_TUNER_STATE(__new_state__) \
{ \
semaphore_wait ( psemTunerStateWriteAccess ); \
tuner_state = __new_state__; \
semaphore_signal ( psemTunerStateWriteAccess ); \
QAM_DEBUG_CODE(do_report ( severity_info, "Force TUNER_STATE changed -> %d\n", __new_state__ )); \
}
/*
* update tuner_state if the current state has not changed,
* this will be invoked only by the tuner_process.
*/
#define UPDATE_TUNER_STATE(__old_state__, __new_state__) \
{ \
semaphore_wait ( psemTunerStateWriteAccess ); \
if ( tuner_state == __old_state__ ) \
{\
tuner_state = __new_state__; \
QAM_DEBUG_CODE(do_report ( severity_info, "TUNER_STATE changed %d -> %d\n",__old_state__,__new_state__ )); \
}\
else\
{ \
DUMMY_CODE; \
QAM_DEBUG_CODE(do_report ( severity_info, "Cannot changed TUNER_STATE %d -> %d , Current TUNER_STATE is %d\n",__old_state__,__new_state__,tuner_state)); \
} \
semaphore_signal ( psemTunerStateWriteAccess ); \
}
/*----------------------------------------------------------------------------*/
#define TUNER_PAUSE \
{ \
FORCE_TUNER_STATE ( TUNER_IDLE ); \
QAM_DEBUG_CODE ( do_report ( severity_info,\
"NEW_REQ => psemTunerIdleStateEntered (%d)\n", psemTunerIdleStateEntered -> semaphore_count ) ); \
semaphore_wait ( psemTunerIdleStateEntered ); \
}
/*----------------------------------------------------------------------------*/
#define TUNER_RESUME \
{ \
FORCE_TUNER_STATE( SIGNAL_DETECTION ); \
semaphore_signal( psemTunerIdleStateReleased ); \
}
/*----------------------------------------------------------------------------*/
#define ENABLE_I2C_REPEATER \
{ \
link_write(CTRL_7,0x2b); \
MILLI_DELAY(30); \
link_write(CTRL_6,0xc0); \
}
/*----------------------------------------------------------------------------*/
#define DISABLE_I2C_REPEATER \
{ \
link_write(CTRL_6,0x40); \
MILLI_DELAY(30); \
link_write(CTRL_7,0x6b); \
}
/*----------------------------------------------------------------------------*/
/* VARIABLES */
static tuner_state_t tuner_state = TUNER_IDLE;
/*
* the tuner_state_write_access_sem should be locked before writing the
* new state of tuner
*/
static semaphore_t *psemTunerStateWriteAccess = NULL;
static semaphore_t *psemTunerIdleStateEntered = NULL;
static semaphore_t *psemTunerIdleStateReleased = NULL;
semaphore_t *psemLinkIcAccess = NULL;
static semaphore_t *psemTunerAccess = NULL;
static unsigned char cQamSize = QAM64;
static int iSymbolRate = 0;
static int iCurTunedFreq = 0;
static int iTransponderFreq;
static int iSweepRate;
static int iFrequencyOffset;
static int iSpectrumInversion;
static task_t *ptidTunerTask;
#define I2C_COMMAND_LEN 6
unsigned char i2c_buffer[ I2C_COMMAND_LEN ];
/*----------------------------------------------------------------------------*/
BOOLEAN link_read ( BYTE reg, BYTE *value_p )
{
BOOLEAN error = FALSE;
int actlen = 1;
semaphore_wait( psemLinkIcAccess );
while(true)
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