uart_top_tb.vhd

《FPGA数字电子系统设计与开发实例导航》的配套光盘

-- 库声明
library ieee;
use work.uart_package.all;
use ieee.std_logic_1164.all;

-- 实体声明
entity uart_top_tb is
	-- 定义类属参数
	generic(
	DATA_BIT : INTEGER := 8;
	TOTAL_BIT : INTEGER := 10;
	PARITY_RULE : PARITY := none;
	FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;		-- 5208 if testing 9600 baudrate
	RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC 		-- 2604 if testing 9600 baudrate
	);
end uart_top_tb;

-- 结构体
architecture TB_ARCHITECTURE of uart_top_tb is

-- UART顶层模块组件声明
component uart_top
	generic(
	DATA_BIT : INTEGER := 8;
	TOTAL_BIT : INTEGER := 10;
	PARITY_RULE : PARITY := none;
	FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;
	RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC );
port(
	RxD : in std_logic;
	clk : in std_logic;
	reset_n : in std_logic;
	send : in std_logic;
	send_bus : in std_logic_vector(7 downto 0);
	TxD : out std_logic;
	error : out std_logic;
	recv : out std_logic;
	send_over : out std_logic;
	recv_bus : out std_logic_vector(7 downto 0) );
end component;

-- 内部信号
signal RxD : std_logic := '1';
signal clk : std_logic := '0';
signal reset_n : std_logic := '0';
signal send : std_logic := '0';
signal send_bus : std_logic_vector(7 downto 0) := (others => '0');
signal TxD : std_logic := '1';
signal error : std_logic := '0';
signal recv : std_logic := '0';
signal send_over : std_logic := '0';
signal recv_bus : std_logic_vector(7 downto 0) := (others => '0');

begin

	-- 测试对象实例化
	UUT : uart_top
		generic map (
			DATA_BIT => DATA_BIT,
			TOTAL_BIT => TOTAL_BIT,
			PARITY_RULE => PARITY_RULE,
			FULL_PULSE_COUNT => BD9600_FPC,
			RISE_PULSE_COUNT => BD9600_HPC
		)

		port map (
			RxD => RxD,
			clk => clk,
			reset_n => reset_n,
			send => send,
			send_bus => send_bus,
			TxD => TxD,
			error => error,
			recv => recv,
			send_over => send_over,
			recv_bus => recv_bus
		);

	-- 产生时钟信号
	clk_gen : process
	begin
		clk <= not clk;
		wait for 10 ns;
	end process;

	-- 测试主流程
	main: process
	begin
		-- 复位
		reset_n <= '0';
		wait for 100 ns;
		
		-- 结束复位
		reset_n <= '1';
		wait for 100 ns;
	
		-- 测试数据发送
		wait for 10 ns;
		-- 发送数据为01010101
		send_bus <= "01010101";
		-- send为高激活数据发送
		send <= '1';
		wait for 20 ns;
		send <= '0';
		
		-- 测试数据接收
		-- 使用测试用波特率
		if FULL_PULSE_COUNT = BDTEST_FPC then
			wait for 2500 ns;
			-- 仿真RS-232输入信号RxD
			for i in 0 to 9 loop
				RxD <= test_si_none(i);
				-- 测试波特率为10，所以输入间隔10个时钟，总共200ns
				wait for 200 ns;
			end loop;
		-- 使用实际波特率9600
		elsif FULL_PULSE_COUNT = BD9600_FPC then
			wait for 1.2 ms;
			-- 仿真RS-232输入信号RxD
			for i in 0 to 9 loop
				RxD <= test_si_none(i);
				-- 测试波特率为9600，所以输入间隔9600个时钟，总共104.17μs
				wait for 104.17 us;
			end loop;
		end if;
	
		wait ;
	end process;

end TB_ARCHITECTURE;

-- 配置
configuration TESTBENCH_FOR_uart_top of uart_top_tb is
	for TB_ARCHITECTURE
		for UUT : uart_top
			use entity work.uart_top(uart_top);
		end for;
	end for;
end TESTBENCH_FOR_uart_top;