baudrate_generator.vhd

《FPGA数字电子系统设计与开发实例导航》的配套光盘

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;

-- 实体声明
entity baudrate_generator is
	-- 类属参数声明
	generic (
	FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;
	RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC );
	-- 端口声明
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	ce : in std_logic;
	bg_out : out std_logic;
	indicator : out std_logic );
	
end baudrate_generator;

--}} End of automatically maintained section
-- 结构体
architecture baudrate_generator of baudrate_generator is
begin

	-- enter your statements here --
	-- 主过程
	-- main process
	main : process( clk, reset_n )
	variable clk_count : BD_COUNT; 
	begin
		-- 判断复位信号
		if reset_n = '0' then
			bg_out <= '0';
			indicator <= '0';
			clk_count := 0;
		-- 在时钟信号的上升沿动作
		elsif rising_edge(clk) then
			-- 判断使能信号
			if ce = '1' then
				-- 经过了RISE_PULSE_COUNT个计数，数脉冲上升
				if clk_count = RISE_PULSE_COUNT-1 then		-- pulse rise
					bg_out <= '1';
					clk_count := clk_count+1;
				-- 经过了FULL_PULSE_COUNT个计数，数脉冲下降
				elsif clk_count = FULL_PULSE_COUNT-1 then	-- indicator output and pulse fall
					-- 输出提示信号，使其为高
					indicator <= '1';
					bg_out <= '0';
					-- 重置计数器计数为0
					clk_count := 0;
				-- 恢复提示信号为低
				elsif clk_count = 0 then
					indicator <= '0';
					clk_count := clk_count+1;
				else
					clk_count := clk_count+1;
				end if;
			end if;
		end if;
	end process;

end baudrate_generator;