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📄 display.tan.rpt

📁 fpga交通控制灯
💻 RPT
📖 第 1 页 / 共 3 页
字号:
; N/A                                     ; None                                                ; 18.474 ns       ; shut2   ; display[4] ;
; N/A                                     ; None                                                ; 18.474 ns       ; led3[3] ; display[1] ;
; N/A                                     ; None                                                ; 18.466 ns       ; led7[0] ; display[2] ;
; N/A                                     ; None                                                ; 18.463 ns       ; led2[3] ; display[2] ;
; N/A                                     ; None                                                ; 18.435 ns       ; led4[0] ; display[2] ;
; N/A                                     ; None                                                ; 18.430 ns       ; led2[0] ; display[4] ;
; N/A                                     ; None                                                ; 18.430 ns       ; shut0   ; display[3] ;
; N/A                                     ; None                                                ; 18.412 ns       ; led3[1] ; display[4] ;
; N/A                                     ; None                                                ; 18.409 ns       ; shut4   ; display[4] ;
; N/A                                     ; None                                                ; 18.408 ns       ; led7[0] ; display[5] ;
; N/A                                     ; None                                                ; 18.389 ns       ; shut3   ; display[5] ;
; N/A                                     ; None                                                ; 18.365 ns       ; led0[1] ; display[3] ;
; N/A                                     ; None                                                ; 18.351 ns       ; led4[1] ; display[4] ;
; N/A                                     ; None                                                ; 18.332 ns       ; shut4   ; display[1] ;
; N/A                                     ; None                                                ; 18.324 ns       ; led3[0] ; display[2] ;
; N/A                                     ; None                                                ; 18.267 ns       ; led7[3] ; display[4] ;
; N/A                                     ; None                                                ; 18.266 ns       ; led2[2] ; display[5] ;
; N/A                                     ; None                                                ; 18.261 ns       ; led6[1] ; display[0] ;
; N/A                                     ; None                                                ; 18.255 ns       ; led0[1] ; display[4] ;
; N/A                                     ; None                                                ; 18.238 ns       ; led4[0] ; display[3] ;
; N/A                                     ; None                                                ; 18.227 ns       ; shut1   ; display[6] ;
; N/A                                     ; None                                                ; 18.211 ns       ; shut0   ; display[4] ;
; N/A                                     ; None                                                ; 18.184 ns       ; led0[0] ; display[5] ;
; N/A                                     ; None                                                ; 18.184 ns       ; led7[1] ; display[0] ;
; N/A                                     ; None                                                ; 18.165 ns       ; shut3   ; display[6] ;
; N/A                                     ; None                                                ; 18.157 ns       ; led3[3] ; display[4] ;
; N/A                                     ; None                                                ; 18.153 ns       ; led3[2] ; display[6] ;
; N/A                                     ; None                                                ; 18.142 ns       ; shut5   ; display[5] ;
; N/A                                     ; None                                                ; 18.115 ns       ; led2[1] ; display[3] ;
; N/A                                     ; None                                                ; 18.115 ns       ; led6[2] ; display[0] ;
; N/A                                     ; None                                                ; 18.098 ns       ; led7[2] ; display[0] ;
; N/A                                     ; None                                                ; 18.082 ns       ; led2[2] ; display[4] ;
; N/A                                     ; None                                                ; 18.079 ns       ; shut1   ; display[5] ;
; N/A                                     ; None                                                ; 18.079 ns       ; led7[3] ; display[2] ;
; N/A                                     ; None                                                ; 18.053 ns       ; led3[0] ; display[1] ;
; N/A                                     ; None                                                ; 18.017 ns       ; led4[0] ; display[1] ;
; N/A                                     ; None                                                ; 18.014 ns       ; led5[1] ; display[4] ;
; N/A                                     ; None                                                ; 18.011 ns       ; led6[0] ; display[0] ;
; N/A                                     ; None                                                ; 18.009 ns       ; led7[3] ; display[5] ;
; N/A                                     ; None                                                ; 18.007 ns       ; led3[2] ; display[5] ;
; N/A                                     ; None                                                ; 17.998 ns       ; led5[1] ; display[0] ;
; N/A                                     ; None                                                ; 17.969 ns       ; led3[2] ; display[0] ;
; N/A                                     ; None                                                ; 17.956 ns       ; shut0   ; display[1] ;
; N/A                                     ; None                                                ; 17.953 ns       ; led5[1] ; display[2] ;
; N/A                                     ; None                                                ; 17.949 ns       ; shut4   ; display[6] ;
; N/A                                     ; None                                                ; 17.915 ns       ; shut6   ; display[0] ;
; N/A                                     ; None                                                ; 17.898 ns       ; shut1   ; display[0] ;
; N/A                                     ; None                                                ; 17.887 ns       ; led4[1] ; display[5] ;
; N/A                                     ; None                                                ; 17.879 ns       ; led5[0] ; display[4] ;
; N/A                                     ; None                                                ; 17.868 ns       ; led5[0] ; display[0] ;
; N/A                                     ; None                                                ; 17.849 ns       ; led4[0] ; display[4] ;
; N/A                                     ; None                                                ; 17.843 ns       ; shut2   ; display[6] ;
; N/A                                     ; None                                                ; 17.840 ns       ; shut0   ; display[5] ;
; N/A                                     ; None                                                ; 17.839 ns       ; shut5   ; display[0] ;
; N/A                                     ; None                                                ; 17.814 ns       ; led5[0] ; display[2] ;
; N/A                                     ; None                                                ; 17.813 ns       ; led7[0] ; display[1] ;
; N/A                                     ; None                                                ; 17.812 ns       ; led7[0] ; display[3] ;
; N/A                                     ; None                                                ; 17.738 ns       ; led3[0] ; display[4] ;
; N/A                                     ; None                                                ; 17.709 ns       ; led0[1] ; display[5] ;
; N/A                                     ; None                                                ; 17.698 ns       ; shut2   ; display[3] ;
; N/A                                     ; None                                                ; 17.664 ns       ; led3[1] ; display[6] ;
; N/A                                     ; None                                                ; 17.611 ns       ; led5[2] ; display[6] ;
; N/A                                     ; None                                                ; 17.605 ns       ; led0[0] ; display[6] ;
; N/A                                     ; None                                                ; 17.601 ns       ; led2[0] ; display[6] ;
; N/A                                     ; None                                                ; 17.596 ns       ; led5[3] ; display[4] ;
; N/A                                     ; None                                                ; 17.574 ns       ; led5[3] ; display[0] ;
; N/A                                     ; None                                                ; 17.556 ns       ; led2[3] ; display[5] ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                 ;         ;            ;
+-----------------------------------------+-----------------------------------------------------+-----------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 15:59:49 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off display -c display --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "count[1]" and destination register "count[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.196 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y18_N0; Fanout = 19; REG Node = 'count[1]'
            Info: 2: + IC(0.589 ns) + CELL(0.607 ns) = 1.196 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count[2]'
            Info: Total cell delay = 0.607 ns ( 50.75 % )
            Info: Total interconnect delay = 0.589 ns ( 49.25 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count[2]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
            Info: - Longest clock path from clock "clk" to source register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X26_Y18_N0; Fanout = 19; REG Node = 'count[1]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "display[3]" through register "count[2]" is 16.434 ns
    Info: + Longest clock path from clock "clk" to source register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count[2]'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 12.964 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count[2]'
        Info: 2: + IC(1.495 ns) + CELL(0.590 ns) = 2.085 ns; Loc. = LC_X26_Y19_N4; Fanout = 1; COMB Node = 'Mux3~58'
        Info: 3: + IC(0.340 ns) + CELL(0.114 ns) = 2.539 ns; Loc. = LC_X26_Y19_N5; Fanout = 1; COMB Node = 'Mux3~59'
        Info: 4: + IC(1.472 ns) + CELL(0.590 ns) = 4.601 ns; Loc. = LC_X27_Y18_N5; Fanout = 1; COMB Node = 'Mux3~60'
        Info: 5: + IC(1.666 ns) + CELL(0.590 ns) = 6.857 ns; Loc. = LC_X23_Y17_N2; Fanout = 1; COMB Node = 'Mux3~64'
        Info: 6: + IC(3.983 ns) + CELL(2.124 ns) = 12.964 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'display[3]'
        Info: Total cell delay = 4.008 ns ( 30.92 % )
        Info: Total interconnect delay = 8.956 ns ( 69.08 % )
Info: Longest tpd from source pin "led1[2]" to destination pin "display[3]" is 22.187 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_C17; Fanout = 7; PIN Node = 'led1[2]'
    Info: 2: + IC(8.025 ns) + CELL(0.442 ns) = 9.936 ns; Loc. = LC_X26_Y21_N4; Fanout = 1; COMB Node = 'decoder:U2|Mux3~39'
    Info: 3: + IC(1.258 ns) + CELL(0.114 ns) = 11.308 ns; Loc. = LC_X26_Y19_N4; Fanout = 1; COMB Node = 'Mux3~58'
    Info: 4: + IC(0.340 ns) + CELL(0.114 ns) = 11.762 ns; Loc. = LC_X26_Y19_N5; Fanout = 1; COMB Node = 'Mux3~59'
    Info: 5: + IC(1.472 ns) + CELL(0.590 ns) = 13.824 ns; Loc. = LC_X27_Y18_N5; Fanout = 1; COMB Node = 'Mux3~60'
    Info: 6: + IC(1.666 ns) + CELL(0.590 ns) = 16.080 ns; Loc. = LC_X23_Y17_N2; Fanout = 1; COMB Node = 'Mux3~64'
    Info: 7: + IC(3.983 ns) + CELL(2.124 ns) = 22.187 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'display[3]'
    Info: Total cell delay = 5.443 ns ( 24.53 % )
    Info: Total interconnect delay = 16.744 ns ( 75.47 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 15:59:50 2008
    Info: Elapsed time: 00:00:01


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