display.tan.rpt

fpga交通控制灯

Classic Timing Analyzer report for display
Fri Nov 14 15:59:50 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. tpd
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From     ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 16.434 ns                                      ; count[2] ; display[3] ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 22.187 ns                                      ; led1[2]  ; display[3] ; --         ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[2]   ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;          ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12F324C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                       ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From     ; To       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.196 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 1.185 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.027 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.906 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.905 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 0.905 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+----------+------------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To         ; From Clock ;
+-------+--------------+------------+----------+------------+------------+
; N/A   ; None         ; 16.434 ns  ; count[2] ; display[3] ; clk        ;
; N/A   ; None         ; 16.325 ns  ; count[2] ; display[0] ; clk        ;
; N/A   ; None         ; 15.725 ns  ; count[1] ; display[3] ; clk        ;
; N/A   ; None         ; 15.720 ns  ; count[2] ; display[1] ; clk        ;
; N/A   ; None         ; 15.153 ns  ; count[1] ; display[1] ; clk        ;
; N/A   ; None         ; 15.043 ns  ; count[1] ; display[6] ; clk        ;
; N/A   ; None         ; 14.983 ns  ; count[1] ; display[0] ; clk        ;
; N/A   ; None         ; 14.769 ns  ; count[2] ; display[2] ; clk        ;
; N/A   ; None         ; 14.536 ns  ; count[2] ; display[4] ; clk        ;
; N/A   ; None         ; 14.356 ns  ; count[1] ; display[2] ; clk        ;
; N/A   ; None         ; 14.327 ns  ; count[2] ; display[6] ; clk        ;
; N/A   ; None         ; 14.045 ns  ; count[2] ; display[5] ; clk        ;
; N/A   ; None         ; 13.981 ns  ; count[1] ; display[4] ; clk        ;
; N/A   ; None         ; 13.919 ns  ; count[1] ; display[5] ; clk        ;
; N/A   ; None         ; 12.277 ns  ; count[0] ; display[4] ; clk        ;
; N/A   ; None         ; 11.598 ns  ; count[0] ; display[3] ; clk        ;
; N/A   ; None         ; 11.529 ns  ; count[0] ; display[2] ; clk        ;
; N/A   ; None         ; 11.412 ns  ; count[0] ; display[6] ; clk        ;
; N/A   ; None         ; 11.394 ns  ; count[0] ; display[1] ; clk        ;
; N/A   ; None         ; 11.361 ns  ; count[0] ; display[0] ; clk        ;
; N/A   ; None         ; 11.352 ns  ; count[0] ; display[5] ; clk        ;
; N/A   ; None         ; 9.688 ns   ; count[2] ; sel_bit[2] ; clk        ;
; N/A   ; None         ; 9.652 ns   ; count[1] ; sel_bit[1] ; clk        ;
; N/A   ; None         ; 9.560 ns   ; count[0] ; sel_bit[0] ; clk        ;
+-------+--------------+------------+----------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+-----------------+---------+------------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From    ; To         ;