display.vhd

来自「fpga交通控制灯」· VHDL 代码 · 共 142 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity display is
	port(clk :in std_logic;
		 flash : in std_logic;
		 shut0,shut1,shut2,shut3,shut4,shut5,shut6,shut7 : in std_logic;
		 led0: in std_logic_vector(3 downto 0);
		 led1: in std_logic_vector(3 downto 0);
	   	 led2: in std_logic_vector(3 downto 0);
		 led3: in std_logic_vector(3 downto 0);
		 led4: in std_logic_vector(3 downto 0);
		 led5: in std_logic_vector(3 downto 0);
		 led6: in std_logic_vector(3 downto 0);
		 led7: in std_logic_vector(3 downto 0);
		 display : out std_logic_vector(6 downto 0);
		 sel_bit : out std_logic_vector(2 downto 0)
		 );
end entity;

architecture beha of display is
component decoder is 
port(led : in std_logic_vector(3 downto 0);
	 decoder_led: out std_logic_vector(6 downto 0));
end component;
signal decoder_led0,decoder_led1,decoder_led2,decoder_led3 : std_logic_vector(6 downto 0);
signal decoder_led4,decoder_led5,decoder_led6,decoder_led7 : std_logic_vector(6 downto 0);
signal count: std_logic_vector(2 downto 0);
signal count1:std_logic_vector(8 downto 0);
signal display_v:std_logic_vector(6 downto 0);
signal z: std_logic:='1';
begin
	U1: decoder port map (led0,decoder_led0);
	U2: decoder port map (led1,decoder_led1);
	U3: decoder port map (led2,decoder_led2);
	U4: decoder port map (led3,decoder_led3);
	U5: decoder port map (led4,decoder_led4);
	U6: decoder port map (led5,decoder_led5);
	U7: decoder port map (led6,decoder_led6);
	U8: decoder port map (led7,decoder_led7);
	
	process(clk)
	begin
		if(rising_edge(clk))then
			if(count="111")then
				count<="000";
			else 
				count<=count+'1';
			end if;
		end if;
	end process;
	
	process(count,decoder_led0,decoder_led1,decoder_led2,decoder_led3,decoder_led4,decoder_led5,decoder_led6,decoder_led7,
			shut0,shut1,shut2,shut3,shut4,shut5,shut6,shut7)
	begin
		case count is
			when "000" => 
				if(shut0='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led0;
				end if;
			when "001" => 
				if(shut1='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led1;
				end if;
			when "010" => 
				if(shut2='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led2;
				end if;
			when "011" => 
   				if(shut3='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led3;
				end if;
			when "100" => 
				if(shut4='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led4;
				end if;
			when "101" => 
				if(shut5='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led5;
				end if;
			when "110" => 
				if(shut6='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led6;
				end if;			
			when "111" => 
				if(shut7='1')then
					display_v<="0000000";
				else
					display_v<=decoder_led7;
				end if;
		end case;
	end process;
	process(count)
	begin
		case count is
			when "000" => sel_bit <= "000";
			when "001" => sel_bit <= "001";
			when "010" => sel_bit <= "010";
			when "011" => sel_bit <= "011";
			when "100" => sel_bit <= "100";
			when "101" => sel_bit <= "101";
			when "110" => sel_bit <= "110";
			when "111" => sel_bit <= "111";
		end case;
	end process;
	process(clk,flash)
	begin
		if(rising_edge(clk))then
			if(count1="111110011")then
				count1<="000000000";
				z<= not z;
			else
				count1<=count1 +'1';
			end if;	
		end if;
		if(flash='0')then
			if(z='1')then
				display<="0000000";
			else
				display<=display_v;
			end if;
		else
			display<=display_v;
		end if;
	end process;
	
end architecture;