display.tan.qmsg

fpga交通控制灯

{ "Info" "ITDB_FULL_TCO_RESULT" "clk display\[3\] count\[2\] 16.434 ns register " "Info: tco from clock \"clk\" to destination pin \"display\[3\]\" through register \"count\[2\]\" is 16.434 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.246 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns count\[2\] 2 REG LC_X26_Y18_N9 32 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { clk count[2] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.964 ns + Longest register pin " "Info: + Longest register to pin delay is 12.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[2\] 1 REG LC_X26_Y18_N9 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y18_N9; Fanout = 32; REG Node = 'count\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[2] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.495 ns) + CELL(0.590 ns) 2.085 ns Mux3~58 2 COMB LC_X26_Y19_N4 1 " "Info: 2: + IC(1.495 ns) + CELL(0.590 ns) = 2.085 ns; Loc. = LC_X26_Y19_N4; Fanout = 1; COMB Node = 'Mux3~58'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { count[2] Mux3~58 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 2.539 ns Mux3~59 3 COMB LC_X26_Y19_N5 1 " "Info: 3: + IC(0.340 ns) + CELL(0.114 ns) = 2.539 ns; Loc. = LC_X26_Y19_N5; Fanout = 1; COMB Node = 'Mux3~59'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { Mux3~58 Mux3~59 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.472 ns) + CELL(0.590 ns) 4.601 ns Mux3~60 4 COMB LC_X27_Y18_N5 1 " "Info: 4: + IC(1.472 ns) + CELL(0.590 ns) = 4.601 ns; Loc. = LC_X27_Y18_N5; Fanout = 1; COMB Node = 'Mux3~60'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { Mux3~59 Mux3~60 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.666 ns) + CELL(0.590 ns) 6.857 ns Mux3~64 5 COMB LC_X23_Y17_N2 1 " "Info: 5: + IC(1.666 ns) + CELL(0.590 ns) = 6.857 ns; Loc. = LC_X23_Y17_N2; Fanout = 1; COMB Node = 'Mux3~64'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.256 ns" { Mux3~60 Mux3~64 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(2.124 ns) 12.964 ns display\[3\] 6 PIN PIN_L5 0 " "Info: 6: + IC(3.983 ns) + CELL(2.124 ns) = 12.964 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'display\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.107 ns" { Mux3~64 display[3] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.008 ns ( 30.92 % ) " "Info: Total cell delay = 4.008 ns ( 30.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.956 ns ( 69.08 % ) " "Info: Total interconnect delay = 8.956 ns ( 69.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.964 ns" { count[2] Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.964 ns" { count[2] Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } { 0.000ns 1.495ns 0.340ns 1.472ns 1.666ns 3.983ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.964 ns" { count[2] Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.964 ns" { count[2] Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } { 0.000ns 1.495ns 0.340ns 1.472ns 1.666ns 3.983ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "led1\[2\] display\[3\] 22.187 ns Longest " "Info: Longest tpd from source pin \"led1\[2\]\" to destination pin \"display\[3\]\" is 22.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns led1\[2\] 1 PIN PIN_C17 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_C17; Fanout = 7; PIN Node = 'led1\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { led1[2] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.025 ns) + CELL(0.442 ns) 9.936 ns decoder:U2\|Mux3~39 2 COMB LC_X26_Y21_N4 1 " "Info: 2: + IC(8.025 ns) + CELL(0.442 ns) = 9.936 ns; Loc. = LC_X26_Y21_N4; Fanout = 1; COMB Node = 'decoder:U2\|Mux3~39'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.467 ns" { led1[2] decoder:U2|Mux3~39 } "NODE_NAME" } } { "comp_decoder/decoder.vhd" "" { Text "D:/VHDL/trafic/display/comp_decoder/decoder.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.114 ns) 11.308 ns Mux3~58 3 COMB LC_X26_Y19_N4 1 " "Info: 3: + IC(1.258 ns) + CELL(0.114 ns) = 11.308 ns; Loc. = LC_X26_Y19_N4; Fanout = 1; COMB Node = 'Mux3~58'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.372 ns" { decoder:U2|Mux3~39 Mux3~58 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 11.762 ns Mux3~59 4 COMB LC_X26_Y19_N5 1 " "Info: 4: + IC(0.340 ns) + CELL(0.114 ns) = 11.762 ns; Loc. = LC_X26_Y19_N5; Fanout = 1; COMB Node = 'Mux3~59'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { Mux3~58 Mux3~59 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.472 ns) + CELL(0.590 ns) 13.824 ns Mux3~60 5 COMB LC_X27_Y18_N5 1 " "Info: 5: + IC(1.472 ns) + CELL(0.590 ns) = 13.824 ns; Loc. = LC_X27_Y18_N5; Fanout = 1; COMB Node = 'Mux3~60'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.062 ns" { Mux3~59 Mux3~60 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.666 ns) + CELL(0.590 ns) 16.080 ns Mux3~64 6 COMB LC_X23_Y17_N2 1 " "Info: 6: + IC(1.666 ns) + CELL(0.590 ns) = 16.080 ns; Loc. = LC_X23_Y17_N2; Fanout = 1; COMB Node = 'Mux3~64'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.256 ns" { Mux3~60 Mux3~64 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(2.124 ns) 22.187 ns display\[3\] 7 PIN PIN_L5 0 " "Info: 7: + IC(3.983 ns) + CELL(2.124 ns) = 22.187 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'display\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.107 ns" { Mux3~64 display[3] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.443 ns ( 24.53 % ) " "Info: Total cell delay = 5.443 ns ( 24.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.744 ns ( 75.47 % ) " "Info: Total interconnect delay = 16.744 ns ( 75.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.187 ns" { led1[2] decoder:U2|Mux3~39 Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.187 ns" { led1[2] led1[2]~out0 decoder:U2|Mux3~39 Mux3~58 Mux3~59 Mux3~60 Mux3~64 display[3] } { 0.000ns 0.000ns 8.025ns 1.258ns 0.340ns 1.472ns 1.666ns 3.983ns } { 0.000ns 1.469ns 0.442ns 0.114ns 0.114ns 0.590ns 0.590ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 15:59:50 2008 " "Info: Processing ended: Fri Nov 14 15:59:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}