decoder.tan.rpt

fpga交通控制灯

Classic Timing Analyzer report for decoder
Fri Nov 14 15:19:39 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                             ;
+------------------------------+-------+---------------+-------------+--------+----------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+----------------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.892 ns   ; led[0] ; decoder_led[4] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;                ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+----------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12F324C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------+
; tpd                                                                   ;
+-------+-------------------+-----------------+--------+----------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To             ;
+-------+-------------------+-----------------+--------+----------------+
; N/A   ; None              ; 10.892 ns       ; led[0] ; decoder_led[4] ;
; N/A   ; None              ; 10.849 ns       ; led[1] ; decoder_led[4] ;
; N/A   ; None              ; 10.822 ns       ; led[0] ; decoder_led[2] ;
; N/A   ; None              ; 10.820 ns       ; led[0] ; decoder_led[6] ;
; N/A   ; None              ; 10.814 ns       ; led[0] ; decoder_led[5] ;
; N/A   ; None              ; 10.814 ns       ; led[0] ; decoder_led[1] ;
; N/A   ; None              ; 10.779 ns       ; led[1] ; decoder_led[2] ;
; N/A   ; None              ; 10.777 ns       ; led[1] ; decoder_led[6] ;
; N/A   ; None              ; 10.776 ns       ; led[1] ; decoder_led[5] ;
; N/A   ; None              ; 10.776 ns       ; led[1] ; decoder_led[1] ;
; N/A   ; None              ; 10.560 ns       ; led[0] ; decoder_led[0] ;
; N/A   ; None              ; 10.522 ns       ; led[1] ; decoder_led[0] ;
; N/A   ; None              ; 10.499 ns       ; led[2] ; decoder_led[4] ;
; N/A   ; None              ; 10.429 ns       ; led[2] ; decoder_led[2] ;
; N/A   ; None              ; 10.428 ns       ; led[2] ; decoder_led[6] ;
; N/A   ; None              ; 10.418 ns       ; led[2] ; decoder_led[5] ;
; N/A   ; None              ; 10.418 ns       ; led[2] ; decoder_led[1] ;
; N/A   ; None              ; 10.374 ns       ; led[0] ; decoder_led[3] ;
; N/A   ; None              ; 10.336 ns       ; led[1] ; decoder_led[3] ;
; N/A   ; None              ; 10.198 ns       ; led[3] ; decoder_led[4] ;
; N/A   ; None              ; 10.164 ns       ; led[2] ; decoder_led[0] ;
; N/A   ; None              ; 10.129 ns       ; led[3] ; decoder_led[2] ;
; N/A   ; None              ; 10.127 ns       ; led[3] ; decoder_led[6] ;
; N/A   ; None              ; 10.125 ns       ; led[3] ; decoder_led[5] ;
; N/A   ; None              ; 10.124 ns       ; led[3] ; decoder_led[1] ;
; N/A   ; None              ; 9.982 ns        ; led[2] ; decoder_led[3] ;
; N/A   ; None              ; 9.871 ns        ; led[3] ; decoder_led[0] ;
; N/A   ; None              ; 9.685 ns        ; led[3] ; decoder_led[3] ;
+-------+-------------------+-----------------+--------+----------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 15:19:39 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder -c decoder --timing_analysis_only
Info: Longest tpd from source pin "led[0]" to destination pin "decoder_led[4]" is 10.892 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_T4; Fanout = 7; PIN Node = 'led[0]'
    Info: 2: + IC(5.575 ns) + CELL(0.114 ns) = 7.164 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; COMB Node = 'Mux2~3'
    Info: 3: + IC(1.620 ns) + CELL(2.108 ns) = 10.892 ns; Loc. = PIN_N8; Fanout = 0; PIN Node = 'decoder_led[4]'
    Info: Total cell delay = 3.697 ns ( 33.94 % )
    Info: Total interconnect delay = 7.195 ns ( 66.06 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 15:19:39 2008
    Info: Elapsed time: 00:00:00